riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
3,755 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

3755 Commits

Author SHA1 Message Date
Clifford Wolf 155a80dfb7 Fix handling of init values in "abc -dff" and "abc -clk" 2017-06-20 15:32:23 +02:00
Clifford Wolf 1f517d2b96 Fix history namespace collision 2017-06-20 05:26:12 +02:00
Clifford Wolf c0ca99483c Store command history when terminating with an error 2017-06-20 04:41:58 +02:00
Clifford Wolf f6421c83a2 Switched abc "clock domain not found" error to log_cmd_error() 2017-06-20 04:22:34 +02:00
Clifford Wolf 8f8baccfde Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand const reg" 2017-06-07 12:30:24 +02:00
Clifford Wolf 129984e115 Fix handling of Verilog ~& and ~| operators 2017-06-01 12:43:21 +02:00
Clifford Wolf 0290b68a44 Update ABC to hg rev efbf7f13ea9e 2017-05-31 11:55:37 +02:00
Clifford Wolf e7a984a4df Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
Clifford Wolf c365e33fd7 Fix AIGER back-end for multiple symbols per input/latch/output/property 2017-05-30 19:09:11 +02:00
Clifford Wolf 05df3dbee4 Add "setundef -anyseq" 2017-05-28 11:59:05 +02:00
Clifford Wolf 9ed4c9d710 Improve write_aiger handling of unconnected nets and constants 2017-05-28 11:31:35 +02:00
Clifford Wolf d9201b85f3 Change default smt2 solver to yices (Yices 2 has switched its license to GPL) 2017-05-27 11:56:01 +02:00
Clifford Wolf fad52abf70 Add aliases for common sets of gate types to "abc -g" 2017-05-24 11:39:05 +02:00
Clifford Wolf dca3b3cd5f Add examples/osu035 2017-05-23 18:38:20 +02:00
Clifford Wolf 664ba4d80e Merge branch 'master' of github.com:cliffordwolf/yosys 2017-05-23 18:24:27 +02:00
Clifford Wolf e0386d04f5 Merge pull request #346 from azonenberg/master 
greenpak4_counters: Added support for parallel output from GP_COUNTx cells
 2017-05-23 14:07:30 +02:00
Andrew Zonenberg 184bd148c9 greenpak4_counters: Added support for parallel output from GP_COUNTx cells 2017-05-22 19:39:55 -07:00
Clifford Wolf 2122ae69b3 Add workaround for CBMC bug to SimpleC back-end 2017-05-17 21:07:54 +02:00
Clifford Wolf 662a047815 Enable readline and tcl in mxe builds 2017-05-17 20:46:22 +02:00
Clifford Wolf 6934b862d3 Add missing AndnotGate() and OrnotGate() declarations to rtlil.h 2017-05-17 19:10:57 +02:00
Clifford Wolf 05cdd58c8d Add $_ANDNOT_ and $_ORNOT_ gates 2017-05-17 09:08:29 +02:00
Clifford Wolf 9f4fbc5e74 Add <modname>_init() function generator to simpleC back-end 2017-05-16 19:34:07 +02:00
Clifford Wolf 35be567605 Improve simplec back-end 2017-05-16 08:50:23 +02:00
Clifford Wolf 8d3c706459 Improve simplec back-end 2017-05-15 13:21:59 +02:00
Clifford Wolf 9c397ea78b Improve simplec back-end 2017-05-14 13:14:49 +02:00
Clifford Wolf 628daab277 Improve simplec back-end 2017-05-13 18:47:31 +02:00
Clifford Wolf ef7594ce3d Improve simplec back-end 2017-05-12 22:39:16 +02:00
Clifford Wolf 7931e1ebb4 Added support for more gate types to simplec back-end 2017-05-12 17:42:31 +02:00
Clifford Wolf bd4ed19887 Add first draft of simple C back-end 2017-05-12 14:13:33 +02:00
Clifford Wolf 241dc7dfb4 Update ABC to hg rev e79576e10d72 2017-05-11 10:32:32 +02:00
Clifford Wolf 1a4b7c6bfa Fix boolector support in yosys-smtbmc 2017-05-08 14:33:22 +02:00
Clifford Wolf e91548b33e Add support for localparam in module header 2017-04-30 17:20:30 +02:00
Clifford Wolf 3bbac5c141 Fix equiv_simple, old behavior now available with "equiv_simple -short" 2017-04-28 18:57:53 +02:00
Clifford Wolf f0db8ffdbc Add support for `resetall compiler directive 2017-04-26 16:09:41 +02:00
Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example) 2017-04-12 16:51:46 +02:00
Larry Doolittle 2021ddecb3 Squelch trailing whitespace 2017-04-12 15:11:09 +02:00
Clifford Wolf 41d4e91f38 Add MAX10 and Cyclone IV items to CHANGELOG 2017-04-07 10:01:28 +02:00
Clifford Wolf 7791888703 Merge pull request #337 from dh73/master 
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
 2017-04-07 09:58:54 +02:00
dh73 c27dcc1e47 Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs 2017-04-05 23:01:29 -05:00
Clifford Wolf fcb274a564 Add ConstEval defaultval feature 2017-04-05 11:25:22 +02:00
Clifford Wolf dee4ec1661 Fix gcc compiler warning 2017-04-05 11:21:06 +02:00
Clifford Wolf b8d7f57f61 Add front-end detection for *.tcl files 2017-03-28 12:13:58 +02:00
Clifford Wolf 58ee8e3b8a Add minisat 00_PATCH_typofixes.patch 2017-03-27 14:37:00 +02:00
Clifford Wolf 71cbe98a09 Remove use of <fpu_control.h> in minisat 2017-03-27 14:32:43 +02:00
Clifford Wolf 106e44f406 Add "write_smt2 -stdt" mode 2017-03-20 12:00:35 +01:00
Clifford Wolf 0ac72e759d Add generation of logic cells to EDIF back-end runtest.py 2017-03-19 14:57:40 +01:00
Clifford Wolf 850f8299a9 Fix EDIF: portRef member 0 is always the MSB bit 2017-03-19 14:53:28 +01:00
Clifford Wolf 1390e9a0a7 Add simple EDIF test case generator and checker 2017-03-18 15:00:03 +01:00
Clifford Wolf 088f9c9cab Fix verilog pre-processor for multi-level relative includes 2017-03-14 17:30:20 +01:00
Clifford Wolf c855353986 Improve smt2 encodings of assert/assume/cover, better wire_smt2 help msg 2017-03-04 23:41:54 +01:00