Clifford Wolf
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d7763634b6
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After reading the SV spec, using non-standard predict() instead of expect()
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2016-07-21 13:34:33 +02:00 |
Clifford Wolf
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721f1f5ecf
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Added basic support for $expect cells
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2016-07-13 16:56:17 +02:00 |
Marcus Comstedt
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e22e4d59b8
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Made the expansion order of hierarchy deterministic
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2016-05-22 16:41:26 +02:00 |
Clifford Wolf
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0bc95f1e04
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Added "yosys -D" feature
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2016-04-21 23:28:37 +02:00 |
Clifford Wolf
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043fa0fad0
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Cleanup abstract modules at end of "hierarchy -top"
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2016-03-21 16:37:35 +01:00 |
Clifford Wolf
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207736b4ee
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Import more std:: stuff into Yosys namespace
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2015-10-25 19:30:49 +01:00 |
Clifford Wolf
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84bf862f7c
|
Spell check (by Larry Doolittle)
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2015-08-14 10:56:05 +02:00 |
Clifford Wolf
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2397078485
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Keep modules with $assume (like $assert)
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2015-07-25 12:09:57 +02:00 |
Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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c52a4cdeed
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Added "dffinit", Support for initialized Xilinx DFF
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2015-04-04 19:00:15 +02:00 |
Clifford Wolf
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4b44907619
|
documentation improvements
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2015-03-29 20:22:08 +02:00 |
Clifford Wolf
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aed4d763cf
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Added hierarchy -auto-top
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2015-03-18 08:33:40 +01:00 |
Clifford Wolf
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ed15400fc6
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Fixed bug in "hierarchy" for parametric designs
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2015-03-04 15:52:34 +01:00 |
Clifford Wolf
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a54c994e2b
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Cosmetic fixes in "hierarchy" for blackbox modules
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2015-02-15 12:57:41 +01:00 |
Clifford Wolf
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0648e2874c
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Fixed pattern matching in "hierarchy -generate"
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2015-01-04 11:45:39 +01:00 |
Clifford Wolf
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a6c96b986b
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Added Yosys::{dict,nodict,vector} container types
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2014-12-26 10:53:21 +01:00 |
Clifford Wolf
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b6a7e21d2e
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Fixed off-by-one bug in "hierarchy -check" for positional module args
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2014-12-24 16:26:18 +01:00 |
Clifford Wolf
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bacd3699b3
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Checking existence of ports in "hierarchy -check"
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2014-12-19 18:47:19 +01:00 |
Clifford Wolf
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51cfcd8331
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Fixed bug in "hierarchy -top" with array of instances
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2014-11-27 12:47:33 +01:00 |
Clifford Wolf
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468ae92374
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Various win32 / vs build fixes
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2014-10-17 14:01:47 +02:00 |
William Speirs
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31267a1ae8
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Header changes so it will compile on VS
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2014-10-17 11:41:36 +02:00 |
Clifford Wolf
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35fbc0b35f
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Do not the 'z' modifier in format string (another win32 fix)
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2014-10-11 11:42:08 +02:00 |
Clifford Wolf
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ee5165c6e4
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Moved patmatch() to yosys.cc
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2014-10-10 18:20:17 +02:00 |
Clifford Wolf
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774933a0d8
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Replaced fnmatch() with patmatch()
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2014-10-10 18:02:17 +02:00 |
Clifford Wolf
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2ee03f5da4
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set "keep" on modules with $assert cells in "hierarchy"
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2014-09-30 19:16:40 +02:00 |
Clifford Wolf
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f9a307a50b
|
namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Ruben Undheim
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79cbf9067c
|
Corrected spelling mistakes found by lintian
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2014-09-06 08:47:06 +02:00 |
Clifford Wolf
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1bf7a18fec
|
Added module->ports
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2014-08-14 16:22:52 +02:00 |
Clifford Wolf
|
768eb846c4
|
More bugfixes related to new RTLIL::IdString
|
2014-08-02 18:14:21 +02:00 |
Clifford Wolf
|
b9bd22b8c8
|
More cleanups related to RTLIL::IdString usage
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2014-08-02 13:19:57 +02:00 |
Clifford Wolf
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e6d33513a5
|
Added module->design and cell->module, wire->module pointers
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2014-07-31 14:11:39 +02:00 |
Clifford Wolf
|
77e2d39cd0
|
Allow "hierarchy -generate" for $__ cells
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2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
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2014-07-28 11:27:48 +02:00 |
Clifford Wolf
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10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
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946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
Clifford Wolf
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f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
744e518467
|
fixed cell array handling of positional arguments
|
2014-06-07 12:17:11 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
cd9e8741a7
|
Implemented read_verilog -defer
|
2014-02-13 13:59:13 +01:00 |
Clifford Wolf
|
7a5f378bae
|
Added hierarchy -purge_lib option
|
2014-02-04 16:50:13 +01:00 |
Martin Schmölzer
|
aa17f16fec
|
Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))
This fixes compilation errors on Arch Linux.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
|
2014-01-14 20:12:45 +01:00 |
Clifford Wolf
|
0c5b1f32d4
|
Added hierarchy -libdir option
|
2014-01-14 19:28:20 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |