riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
1,934 Commits 87 Branches 48 Tags 35 MiB
Commit Graph

1934 Commits

Author SHA1 Message Date
Clifford Wolf e8c66ee36b Fixed MXE readline support 2014-10-11 10:59:11 +02:00
Clifford Wolf 53349fb634 Fixed ifdefs for plugin unloading 2014-10-11 10:57:46 +02:00
Clifford Wolf 51b1824979 Disabled "cover -d" on win32 2014-10-11 10:49:43 +02:00
Clifford Wolf 7df8cbe2a9 Not using std::to_string in ezsat (problems with mingw) 2014-10-11 10:46:50 +02:00
Clifford Wolf 0a651f112f Disabled vhdl2verilog command for win32 builds 2014-10-11 10:46:19 +02:00
Clifford Wolf 93e6ebe771 Disabled ezminisat timeout feature for Win32 2014-10-11 10:24:46 +02:00
Clifford Wolf df537a216b Using next_token() to parse commands 2014-10-10 18:53:03 +02:00
Clifford Wolf 20d85f20db Fixed next_token() 2014-10-10 18:38:40 +02:00
Clifford Wolf 54bf3a95dd More Win32 build fixes 2014-10-10 18:34:19 +02:00
Clifford Wolf 2c683102be Added next_token() function (strtok() replacement) 2014-10-10 18:33:55 +02:00
Clifford Wolf 986bcc13cb Various win32 build fixes in yosys.cc 2014-10-10 18:20:17 +02:00
Clifford Wolf ee5165c6e4 Moved patmatch() to yosys.cc 2014-10-10 18:20:17 +02:00
Clifford Wolf 774933a0d8 Replaced fnmatch() with patmatch() 2014-10-10 18:02:17 +02:00
Clifford Wolf bbd808072b Added format __attribute__ to stringf() 2014-10-10 17:22:08 +02:00
Clifford Wolf 7cb0d3aa1a Renamed TRUE/FALSE to CONST_TRUE/CONST_FALSE because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf 4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf c7f5aab625 Replaced "#ifdef WIN32" with "#ifdef _WIN32" 2014-10-09 17:00:54 +02:00
Clifford Wolf fea11f0fa4 Added API for generic cell cost calculations 2014-10-09 13:59:26 +02:00
Clifford Wolf 1007f54235 added .exe and .html output files to .gitignore 2014-10-09 10:52:45 +02:00
Clifford Wolf d3405c15bf No rusage on win32 2014-10-09 10:51:24 +02:00
Clifford Wolf ccf7b2e342 Added mxe-based cross build for win32 2014-10-09 10:50:44 +02:00
Clifford Wolf 696d7ed40e Fixes in "hilomap" help message 2014-10-08 21:38:37 +02:00
Clifford Wolf 9dea161321 sort cell types in "stat" output by name 2014-10-03 19:21:04 +02:00
Clifford Wolf c5c7066ea6 sat encoding for exclusive $pmux ctrl inputs in "share" pass 2014-10-03 19:01:24 +02:00
Clifford Wolf 56c1d43408 satgen import sigbit api 2014-10-03 18:51:50 +02:00
Clifford Wolf 3e4b0cac8d added resource sharing of $macc cells 2014-10-03 12:58:40 +02:00
Clifford Wolf c3e779a65f Added $_BUF_ cell type 2014-10-03 10:12:28 +02:00
Clifford Wolf 600c6cb013 remove buffers in opt_clean 2014-10-03 10:04:15 +02:00
Clifford Wolf 7019bc00e4 resource sharing of $alu cells 2014-10-03 09:55:50 +02:00
Clifford Wolf 2ee03f5da4 set "keep" on modules with $assert cells in "hierarchy" 2014-09-30 19:16:40 +02:00
Clifford Wolf 0b8cfbc6fd Added support for "keep" on modules 2014-09-29 12:51:54 +02:00
Clifford Wolf f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf bcd2625a82 Merge pull request #39 from ahmedirfan1983/master 
merged with current mas.ter branch + features added + bug fixes
 2014-09-22 12:37:43 +02:00
Ahmed Irfan d3c67ad9b6 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor 
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc
 2014-09-22 11:35:04 +02:00
Clifford Wolf 13117bb346 Re-enabled assert for new logic loops in "share" pass 2014-09-21 19:44:08 +02:00
Clifford Wolf 96e821dc6c Various improvements regarding logic loops in "share" results 2014-09-21 19:36:56 +02:00
Clifford Wolf d6e2ace95b Logic loop bugfix for "share" pass 2014-09-21 15:13:44 +02:00
Clifford Wolf b28be0759f Added "share -limit" 2014-09-21 15:13:06 +02:00
Clifford Wolf a6c08b40fe Still loop bug in "share": changed assert to warning 2014-09-21 14:51:07 +02:00
Clifford Wolf 8d60754aef Do not introduce new logic loops in "share" 2014-09-21 13:52:39 +02:00
Clifford Wolf edf11c635a Assert on new logic loops in "share" pass 2014-09-21 12:57:33 +02:00
Clifford Wolf a7758ef953 Added "test_abcloop" command 2014-09-19 15:51:34 +02:00
Clifford Wolf 00964f2f61 Initialize RTLIL::Const from std::vector<bool> 2014-09-19 15:50:55 +02:00
Clifford Wolf 309623ff17 Sorting of object names in ilang backend 2014-09-19 15:50:34 +02:00
Clifford Wolf 5827826098 Small improvements in "abc" command handle_loops() function 2014-09-19 14:05:41 +02:00
Clifford Wolf 3aa003c8e9 Using "NOT" instead of "INV" as cell name in default abc genlib file 2014-09-19 13:15:31 +02:00
Clifford Wolf f7bb8f244b Alphabetically sort port names in "show" output 2014-09-19 11:13:10 +02:00
Clifford Wolf f56b92818b Do not run "scorr" in "abc -fast" 2014-09-18 19:00:21 +02:00
Clifford Wolf 4888d61c65 Improvements in "synth" script 2014-09-18 12:57:55 +02:00
Clifford Wolf 815fab9d71 Added "abc -fast" 2014-09-18 12:57:37 +02:00