riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
2,642 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

275 Commits

Author SHA1 Message Date
Andrew Zonenberg 7498ff8041 Fixed incorrect port name in cells_map.v 2016-03-31 22:51:22 -07:00
Andrew Zonenberg c04a3d2763 Fixed typo (wasn't written in 2012) 2016-03-30 23:58:45 -07:00
Clifford Wolf d31c968d76 Fixed typo in greenpak4_counters.cc 2016-03-31 08:00:59 +02:00
Andrew Zonenberg 984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Andrew Zonenberg 1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. 2016-03-30 22:40:14 -07:00
Andrew Zonenberg 94a6923e7d Updated tech lib for greenpak4 counter with some clarifications 2016-03-30 20:30:25 -07:00
Andrew Zonenberg 489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start 2016-03-30 01:07:20 -07:00
Andrew Zonenberg 3ea6026648 Added splitnets to synth_greenpak4 2016-03-29 20:02:59 -07:00
Clifford Wolf 19c20235b5 Added more cell help messages 2016-03-29 15:14:43 +02:00
Clifford Wolf 8c8b2e72b1 Fixed indenting in techlibs/greenpak4/gp_dff.lib 2016-03-29 13:44:14 +02:00
Andrew Zonenberg 75f0030458 Added keep constraint to GP_SYSRESET cell 2016-03-28 23:16:43 -07:00
Andrew Zonenberg ea9cc03092 Added GP_SYSRESET block 2016-03-28 22:49:46 -07:00
Andrew Zonenberg 3197b6c372 Added GP_COUNT8/GP_COUNT14 cells 2016-03-26 23:29:02 -07:00
Andrew Zonenberg 31a7567aff Changed GP_LFOSC parameter configuration 2016-03-26 14:13:52 -07:00
Andrew Zonenberg 44fd3cd149 Added GP_LFOSC cell 2016-03-26 13:42:53 -07:00
Andrew Zonenberg af15b92c86 Renamed GP4_V* cells to GP_V* for consistency 2016-03-26 13:42:41 -07:00
Clifford Wolf b4bf787f10 Added GP_DFFS, GP_DFFR, and GP_DFFSR 2016-03-23 08:46:10 +01:00
Clifford Wolf 456c10f16e Added GP_DFF INIT parameter 2016-03-23 08:12:54 +01:00
Clifford Wolf ca8f8e30f2 Improvements in synth_greenpak4, added -part option 2016-03-21 09:44:52 +01:00
Clifford Wolf ff5c61b120 Added black box modules for all the 7-series design elements (as listed in ug953) 2016-03-19 11:09:10 +01:00
Clifford Wolf a75f94ec4a Run dffsr2dff in synth_xilinx 2016-02-13 08:20:19 +01:00
Clifford Wolf 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf bd10927f45 Progress in cell library documentation 2016-02-01 13:58:10 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 2ee608246f Re-run ice40_opt in "synth_ice40 -abc2" 2015-12-22 12:19:11 +01:00
Clifford Wolf 3102ffbb83 Improvements in ice40_opt 2015-12-22 12:18:38 +01:00
Clifford Wolf 8bf452c364 Bugfix in ice40_ffinit 2015-12-22 12:18:06 +01:00
Clifford Wolf ec93d258a4 Improved ice40_ffinit 2015-12-22 11:15:25 +01:00
Clifford Wolf f1b959dc69 Run opt_const before check in default scripts 2015-12-22 11:15:05 +01:00
Clifford Wolf 494e5f24f9 Added "synth_ice40 -abc2" 2015-12-08 11:16:26 +01:00
Clifford Wolf 4d0a6dac7b Merge pull request #108 from cseed/master 
Added LO to ICESTORM_LC for LUT cascade route.
 2015-12-07 03:32:20 +01:00
Cotton Seed 9f5b6e4cbc Added LO to ICESTORM_LC for LUT cascade route. 2015-12-06 17:24:48 -05:00
Clifford Wolf 0793f1b196 Added ice40_ffinit pass 2015-11-26 18:11:06 +01:00
Clifford Wolf 8ff229a3ea Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
Clifford Wolf 3ad742056b Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling 2015-11-06 17:02:16 +01:00
Clifford Wolf 864808992b Bugfix in Xilinx LUT mapping 2015-10-30 13:58:03 +01:00
Clifford Wolf bbcbf739e6 Progress on cell help messages 2015-10-20 16:49:11 +02:00
Clifford Wolf 5d1c0ce7c0 Progress on cell help messages 2015-10-17 02:35:19 +02:00
Clifford Wolf 25c1f6e605 Added "prep" command 2015-10-14 22:46:41 +02:00
Clifford Wolf 87adb523aa Added more cell descriptions 2015-10-14 20:30:59 +02:00
Clifford Wolf 7d3a3a3173 Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Clifford Wolf f42218682d Added examples/ top-level directory 2015-10-13 15:41:20 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf 598a475724 Added nlutmap 2015-09-18 21:57:34 +02:00
Clifford Wolf 745d56149d Renamed GreenPAK4 cells, improved GP4 DFF mapping 2015-09-18 12:00:37 +02:00
Clifford Wolf d9cecabb87 Fixed copy&paste typo in synth_greenpak4 2015-09-16 09:39:31 +02:00
Clifford Wolf c5352f45c3 Added GreenPAK4 skeleton 2015-09-16 09:28:37 +02:00
Clifford Wolf 99ccb3180d Fixed ice40 handling of negclk RAM40 2015-09-10 17:35:19 +02:00
Clifford Wolf c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00