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14425 Commits

Author SHA1 Message Date
KrystalDelusion 6f3376cbe6
Merge pull request #4730 from YosysHQ/krys/downstream-docs 
Improvements for downstream-distro maintainability.
 2024-11-28 14:35:16 +13:00
github-actions[bot] 87742fa688 Bump version 2024-11-28 01:26:26 +00:00
Martin Povišer 646c5a19a8
Merge pull request #4776 from YosysHQ/krys/get_blackbox_attribute 
Move get_blackbox_attribute method to Module instead of AttrObject
 2024-11-28 00:25:16 +01:00
Martin Povišer 1717a0b9c0
Merge pull request #4721 from ldoolitt/main 
kernel/drivertools.h: avoid maybe-uninitialized compile warnings
 2024-11-28 00:09:43 +01:00
Martin Povišer 956313efe8
Merge pull request #4742 from YosysHQ/hierarchy_notify_top_attr 
Print a note about finding attribute (* top *) in hierarchy
 2024-11-28 00:07:18 +01:00
Martin Povišer 3bab837bc9
Merge pull request #4765 from georgerennie/george/rtlil_case_rule 
read_rtlil: Warn on assigns after switches in case rules
 2024-11-28 00:01:21 +01:00
KrystalDelusion 698c464109
Merge pull request #4767 from YosysHQ/krys/latest-compilers 
test-compile: Use newer clang and gcc versions
 2024-11-28 11:51:38 +13:00
KrystalDelusion f428163252
Move get_blackbox_attribute method to Module instead of AttrObject 2024-11-28 11:19:16 +13:00
github-actions[bot] 98b4affc4a Bump version 2024-11-26 01:25:27 +00:00
KrystalDelusion 1e0e367aed
test-compile: Drop back to gcc-13 2024-11-26 10:18:09 +13:00
KrystalDelusion 6ff5823d6a
test-compile: Use clang-18 and gcc-14 
The 'newest' compilers are actually not all that new, they're just the default for the image.  Instead provide explicit versions.
 2024-11-26 09:59:52 +13:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Miodrag Milanović 9512ec4bbc
Merge pull request #4764 from YosysHQ/micko/verific_vhdl_assert 
verific : VHDL assert DFF initial value set on Verific library patch
 2024-11-25 15:06:36 +01:00
George Rennie 8148ebd1ad docs: document that assigns must come before switches in case rules 2024-11-21 22:41:13 +01:00
George Rennie 4a057b3c44 read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
github-actions[bot] 4b3c03dabc Bump version 2024-11-21 00:21:49 +00:00
George Rennie 18b616578a pyosys: catch boost::python::error_already_set 
* This catches exceptions from internal passes, printing them in a
  readable manner where the user would otherwise see an unspecified
  boost exception
 2024-11-20 17:54:11 +01:00
Emil J 5b6baa3ef1
Merge pull request #4744 from YosysHQ/emil/clockgate-liberty 
clockgate: add -liberty
 2024-11-20 15:04:00 +01:00
Martin Povišer 53a4ec375b
Merge pull request #4762 from georgerennie/george/fix_read_ilang_test 
tests: replace read_ilang with read_rtlil
 2024-11-20 14:58:16 +01:00
George Rennie 9043dc0ad6
tests: replace read_ilang with read_rtlil 
* #4612 was written before read_ilang was deprecated but merged after so caused test failures. This switches read_ilang to read_rtlil
 2024-11-20 14:54:23 +01:00
Emil J 56b80bdd22
Merge pull request #4448 from georgerennie/shiftadd_gating 
peepopt shiftadd: Only match for sufficiently small constant widths
 2024-11-20 13:34:09 +01:00
Emil J da8c8b4fd0
Merge pull request #4701 from georgerennie/george/pyosys_noreturn_attrs 
pyosys generator: ignore attributes
 2024-11-20 13:33:33 +01:00
Emil J cc17d5bb70
Merge pull request #4612 from georgerennie/george/opt_demorgan_zero_width 
opt_demorgan: skip zero width cells
 2024-11-20 13:33:16 +01:00
Emil J 18459b4b09
Merge pull request #4614 from georgerennie/george/opt_reduce_cell_width 
opt_reduce: keep at least one input to $reduce_or/and cells
 2024-11-20 13:33:04 +01:00
Emil J 88abc4c20f
Merge pull request #4755 from pepijndevos/cells_xtra 
Gowin: add GW2A and GW5A cells
 2024-11-20 13:32:30 +01:00
Martin Povišer 7ebe451f9a
Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs 
proc_dff: fix early return bug
 2024-11-20 13:26:32 +01:00
Martin Povišer 1184418cc8
Merge pull request #4739 from hzeller/feature-20241113-stdlib-for-abort 
Include stdlib.h for `abort()`
 2024-11-20 10:19:31 +01:00
Krystine Sherwin e649c1a8e1
Docs: Accept empty string for release envvar 2024-11-20 12:31:12 +13:00
Krystine Sherwin 44b68fb498
Docs: Add check for envvar to disable todos 2024-11-20 12:18:17 +13:00
github-actions[bot] b89bd027a0 Bump version 2024-11-19 00:21:56 +00:00
KrystalDelusion dcff8b0666
Merge pull request #4719 from AdamLee7/main 
add select option for write_json
 2024-11-19 08:42:38 +13:00
Emil J. Tywoniak 4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
KrystalDelusion 22e214ec6d
Merge pull request #4705 from YosysHQ/docs-preview-lintonly 
Emphasise that read_verilog doesn't lint
 2024-11-19 03:57:01 +13:00
Martin Povišer 270846a49a
Merge pull request #4723 from povik/memv2-nordports 
rtlil: Adjust internal check for `$mem_v2` cells
 2024-11-18 15:44:39 +01:00
Martin Povišer 1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions 
read_liberty extensions
 2024-11-18 14:42:18 +01:00
Emil J. Tywoniak 983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Emil J. Tywoniak b08441d95c clockgate: shuffle test liberty to exercise comparison better 2024-11-18 12:48:50 +01:00
Emil J. Tywoniak 1e3f8cc630 clockgate: add test liberty file 2024-11-18 12:45:27 +01:00
Emil J. Tywoniak c921d85a85 clockgate: fix test comments 2024-11-18 12:33:09 +01:00
Miodrag Milanović bd40805d54
Merge pull request #4754 from akashlevy/editline-fixes 
Fix `editline` Makefile
 2024-11-18 09:20:45 +01:00
Akash Levy 47a2a09e89 Enforce mutual exclusion on readline/editline 2024-11-17 23:23:37 -08:00
github-actions[bot] 532d5992fd Bump version 2024-11-18 00:22:55 +00:00
Martin Povišer 020dd0a9e7
Merge pull request #4753 from akashlevy/write_verilog_port_dump_fix 
`write_verilog`: Fix `O(N^2)` port dumping to `O(N)`
 2024-11-17 23:42:23 +01:00
Akash Levy ace558e90c Simplify using module->ports, which is apparently sorted 2024-11-17 11:36:30 -08:00
Pepijn de Vos b8329df1d0 add GW2A and GW5A cells 2024-11-17 20:25:11 +01:00
Akash Levy 56f841d132 Fix editline 2024-11-17 10:44:05 -08:00
Akash Levy 3a32729373 Remove keep_running variable (unused) 2024-11-17 10:40:04 -08:00