mirror of https://github.com/YosysHQ/yosys.git
clockgate: shuffle test liberty to exercise comparison better
This commit is contained in:
parent
1e3f8cc630
commit
b08441d95c
|
@ -1,21 +1,5 @@
|
|||
library(test) {
|
||||
/* Integrated clock gating cells */
|
||||
cell (pos_big) {
|
||||
area : 10;
|
||||
clock_gating_integrated_cell : latch_posedge;
|
||||
pin (GCLK) {
|
||||
clock_gate_out_pin : true;
|
||||
direction : output;
|
||||
}
|
||||
pin (CLK) {
|
||||
clock_gate_clock_pin : true;
|
||||
direction : input;
|
||||
}
|
||||
pin (CE) {
|
||||
clock_gate_enable_pin : true;
|
||||
direction : input;
|
||||
}
|
||||
}
|
||||
cell (pos_small_tielo) {
|
||||
area : 1;
|
||||
clock_gating_integrated_cell : latch_posedge_precontrol;
|
||||
|
@ -36,6 +20,22 @@ library(test) {
|
|||
direction : input;
|
||||
}
|
||||
}
|
||||
cell (pos_big) {
|
||||
area : 10;
|
||||
clock_gating_integrated_cell : latch_posedge;
|
||||
pin (GCLK) {
|
||||
clock_gate_out_pin : true;
|
||||
direction : output;
|
||||
}
|
||||
pin (CLK) {
|
||||
clock_gate_clock_pin : true;
|
||||
direction : input;
|
||||
}
|
||||
pin (CE) {
|
||||
clock_gate_enable_pin : true;
|
||||
direction : input;
|
||||
}
|
||||
}
|
||||
cell (pos_small) {
|
||||
area : 1;
|
||||
clock_gating_integrated_cell : latch_posedge;
|
||||
|
|
Loading…
Reference in New Issue