mirror of https://github.com/YosysHQ/yosys.git
clockgate: reduce errors to warnings
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parent
983c54c75f
commit
4d96cbec75
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@ -107,22 +107,25 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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continue;
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if (auto clk = pin->find("clock_gate_clock_pin")) {
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if (!icg_interface.clk_in_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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if (!icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n",
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cell_name.c_str());
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else
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continue;
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} else
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icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto gclk = pin->find("clock_gate_out_pin")) {
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if (!icg_interface.clk_out_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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if (!icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n",
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cell_name.c_str());
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else
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continue;
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} else
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icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto en = pin->find("clock_gate_enable_pin")) {
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if (!icg_interface.ce_pin.empty())
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log_error("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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if (!icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n",
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cell_name.c_str());
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else
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continue;
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} else
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icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]);
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} else if (auto se = pin->find("clock_gate_test_pin")) {
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icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0]));
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@ -131,20 +134,27 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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if (dir->value == "internal")
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continue;
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log_error("Malformed liberty file - extra pin %s in cell %s\n",
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log_warning("Malformed liberty file - extra pin %s in cell %s\n",
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pin->args[0].c_str(), cell_name.c_str());
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continue;
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}
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}
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if (icg_interface.clk_in_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
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if (icg_interface.clk_in_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_clock_pin in cell %s",
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cell_name.c_str());
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if (icg_interface.clk_out_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_out_pin in cell %s",
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continue;
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}
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if (icg_interface.clk_out_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_out_pin in cell %s",
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cell_name.c_str());
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if (icg_interface.ce_pin.empty())
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log_error("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
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continue;
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}
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if (icg_interface.ce_pin.empty()) {
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log_warning("Malformed liberty file - missing clock_gate_enable_pin in cell %s",
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cell_name.c_str());
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continue;
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}
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double area = 0;
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const LibertyAst *ar = cell->find("area");
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@ -179,11 +189,11 @@ static std::pair<std::optional<ClockGateCell>, std::optional<ClockGateCell>>
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std::optional<ClockGateCell> pos;
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std::optional<ClockGateCell> neg;
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if (best_pos) {
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log("Selected rising edge ICG %s\n", best_pos->name.c_str());
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log("Selected rising edge ICG %s from Liberty file\n", best_pos->name.c_str());
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pos.emplace(*best_pos);
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}
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if (best_neg) {
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log("Selected falling edge ICG %s\n", best_neg->name.c_str());
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log("Selected falling edge ICG %s from Liberty file\n", best_neg->name.c_str());
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neg.emplace(*best_neg);
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}
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return std::make_pair(pos, neg);
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