mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4714 from georgerennie/george/proc_dff_bug_multiple_sigs
proc_dff: fix early return bug
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commit
7ebe451f9a
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@ -262,7 +262,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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{
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log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
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gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
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return;
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continue;
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}
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// If there is a reset condition in the async rules, use it
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@ -277,7 +277,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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sync_edge->type == RTLIL::SyncType::STp,
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sync_level && sync_level->type == RTLIL::SyncType::ST1,
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sync_edge->signal, sync_level->signal, proc);
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return;
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continue;
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}
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gen_dff(mod, insig, rstval.as_const(), sig_q,
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@ -0,0 +1,31 @@
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read_rtlil <<EOT
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autoidx 1
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module \top
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wire input 1 \clk
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wire input 2 \rst
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wire input 3 \a_r
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wire input 4 \a_n
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wire input 5 \b_n
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wire \a
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wire \b
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process $proc
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sync high \rst
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update \a \a_r
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update \b \b
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sync posedge \clk
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update \a \a_n
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update \b \b_n
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end
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end
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EOT
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proc_dff
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proc_clean
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# Processes should have been converted to one aldff and one dff
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select -assert-none p:*
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select -assert-count 1 t:$aldff
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select -assert-count 1 t:$dff
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