121 Commits

Author	SHA1	Message	Date
Clifford Wolf	cc4f10883b	Renamed RTLIL::{Module,Cell}::connections to connections_	2014-07-26 11:58:03 +02:00
Clifford Wolf	5826670009	Various RTLIL::SigSpec related code cleanups	2014-07-25 14:25:42 +02:00
Clifford Wolf	28b3fd05fa	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()	2014-07-22 20:58:44 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	f7bd0a5232	Use log_abort() and log_assert() in BTOR backend	2014-03-07 15:56:10 +01:00
Ahmed Irfan	1d64b3e008	register output corrected	2014-02-11 13:28:05 +01:00
Ahmed Irfan	e8f6b8f201	added concat and slice cell translation	2014-02-11 13:06:01 +01:00
Clifford Wolf	f4f230d7cc	Fixed gcc compiler warnings with release build	2014-02-06 22:49:14 +01:00
Clifford Wolf	583636f0ad	Added BTOR backend README file	2014-02-05 18:31:10 +01:00
Clifford Wolf	a6750b3753	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	2014-02-03 13:01:45 +01:00
Ahmed Irfan	0325efe172	root bug corrected	2014-01-25 19:33:24 +01:00
Ahmed Irfan	137742786e	removed regex include	2014-01-24 18:04:37 +01:00
Ahmed Irfan	2e44b1b73a	merged clifford changes + removed regex	2014-01-24 17:35:42 +01:00
Ahmed Irfan	aa3cb20e1e	slice bug corrected	2014-01-20 18:35:52 +01:00
Ahmed Irfan	c347f2825f	assert feature	2014-01-20 10:45:02 +01:00
Ahmed Irfan	9a689f33a5	verilog default options pull ... shift operator width issues	2014-01-17 19:32:35 +01:00
Ahmed Irfan	c7a2e582aa	slice error corrected	2014-01-16 20:16:01 +01:00
Ahmed Irfan	3a1490888d	width issues ... dff cell for more than one registers	2014-01-15 17:36:33 +01:00
Ahmed Irfan	661b5a993e	BTOR backend	2014-01-14 12:03:53 +01:00
Ahmed Irfan	ffd768ce86	btor	2014-01-03 10:52:44 +01:00