Jannis Harder
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6ae0b51c76
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Merge pull request #3287 from jix/smt2-conditional-store
smt2: Make write port array stores conditional on nonzero write mask
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2022-04-25 16:23:21 +02:00 |
Jannis Harder
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e0e31bfc5c
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Merge pull request #3257 from jix/tribuf-formal
tribuf: `-formal` option: convert all to logic and detect conflicts
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2022-04-25 16:23:06 +02:00 |
Miodrag Milanović
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3c0f3504c6
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Merge pull request #3290 from mpasternacki/bugfix/freebsd-build
Fix build on FreeBSD, which has no alloca.h
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2022-04-25 10:16:50 +02:00 |
Miodrag Milanović
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a511c27eb7
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Merge pull request #3289 from YosysHQ/micko/sim_improve
Simulation improvements
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2022-04-25 10:16:25 +02:00 |
Maciej Pasternacki
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0302e97ebc
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Fix build on FreeBSD, which has no alloca.h
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2022-04-24 19:35:50 +02:00 |
Miodrag Milanovic
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bbfdea2f8a
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Match $anyseq input if connected to public wire
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2022-04-22 17:20:17 +02:00 |
Miodrag Milanovic
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4d80bc24c7
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Treat $anyseq as input from FST
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2022-04-22 16:23:39 +02:00 |
Miodrag Milanovic
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9c7deabf94
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Ignore change on last edge
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2022-04-22 15:24:02 +02:00 |
Miodrag Milanovic
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33f4009bb5
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Last sample from input does not represent change
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2022-04-22 13:46:11 +02:00 |
Miodrag Milanovic
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83cad82b29
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latches are always set to zero
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2022-04-22 12:04:05 +02:00 |
Miodrag Milanovic
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c989adcc2d
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If not multiclock, output only on clock edges
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2022-04-22 12:03:39 +02:00 |
Miodrag Milanovic
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75032a565d
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Set init state for all wires from FST and set past
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2022-04-22 11:57:39 +02:00 |
Miodrag Milanovic
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8fa2f3b260
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Fix multiclock for btor2 witness
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2022-04-22 11:53:41 +02:00 |
Jannis Harder
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c7ef0f2932
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smt2: Make write port array stores conditional on nonzero write mask
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2022-04-20 17:49:48 +02:00 |
github-actions[bot]
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29c0a59589
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Bump version
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2022-04-19 00:14:02 +00:00 |
Miodrag Milanović
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c3a3f68b4d
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Merge pull request #3280 from YosysHQ/micko/fix_readaiw
Fix reading aiw from other solvers
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2022-04-18 09:49:21 +02:00 |
Miodrag Milanovic
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2610b04033
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Update abc
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2022-04-18 09:27:00 +02:00 |
Miodrag Milanovic
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1cc281ca6f
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verific: allow memories to be inferred in loops (vhdl)
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2022-04-18 09:10:28 +02:00 |
Miodrag Milanović
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d23260d381
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Merge pull request #3282 from nakengelhardt/verific_loop_rams
verific: allow memories to be inferred in loops
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2022-04-18 09:09:36 +02:00 |
github-actions[bot]
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36b5caf821
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Bump version
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2022-04-16 00:14:57 +00:00 |
Marcelina Kościelnicka
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25ff83f0b5
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memory_share: Fix up mismatched address widths.
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2022-04-15 22:01:00 +02:00 |
Marcelina Kościelnicka
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48eea3efcf
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opt_dff: Fix behavior on $ff with D == Q.
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2022-04-15 22:00:32 +02:00 |
N. Engelhardt
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57bc29c64a
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verific: allow memories to be inferred in loops
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2022-04-15 15:10:48 +02:00 |
Miodrag Milanovic
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9508bb2330
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Fix reading aiw from other solvers
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2022-04-15 11:45:16 +02:00 |
Jannis Harder
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bc48500548
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tribuf: `-formal` option: convert all to logic and detect conflicts
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2022-04-12 12:46:22 +02:00 |
github-actions[bot]
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c1646a00ac
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Bump version
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2022-04-09 00:15:22 +00:00 |
Miodrag Milanović
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4772bc70d0
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Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
Use wrap_async_control_gate if ff is fine
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2022-04-08 17:38:54 +02:00 |
Miodrag Milanovic
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868409361c
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Use wrap_async_control_gate if ff is fine
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2022-04-08 16:30:29 +02:00 |
Miodrag Milanović
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bd7ee79486
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Merge pull request #3273 from modwizcode/fix-build
Do not enable features that require the support of compression compiled in
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2022-04-08 10:08:05 +02:00 |
Aki Van Ness
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1f1a403cce
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pass jny: flipped the defaults for the inclusion of various bits of metadata
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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6053856f91
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pass jny: ensured the cell collection is cleared between modules
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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5a016713cc
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pass jny: fixed missing quotes around the type value for the cell sort
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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2e792857e9
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pass jny: fixed the backslash escape for strings
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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cae5ea8337
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pass jny: removed the invalid json escapes
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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dccc89e8b3
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pass jny: added some todo comments about things that need to be done before a proper merge, but it should be enough for the PoC at the moment
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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1be9bef28b
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pass jny: changed the constructor initializers to use parens rather than curly-braces to hopefully make GCC 4.8 happy
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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43b2fc5566
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pass jny: fixed the string escape method to be less jank and more proper
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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52ea944012
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pass jny: fixed the signed output for param value output
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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58e2870261
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pass jny: added connection output
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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167206f2f5
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pass jny: added filter options for including connections, attributes, and properties
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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587f31b9a3
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pass jny: large chunk of refactoring to make the JSON output more pretty and the internals less of a spaghetti nightmare
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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0e20619189
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metadata -> jny: migrated to the proper name for the pass
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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bdf14557ca
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pass metadata: added the machinery to write param and attributes
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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1876ed21e7
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pass metadata: removed superfluous `stringf` calls
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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ca03fbdc6d
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pass metadata: some more rough work on dumping the parameters and attributes
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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6a90b42c48
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pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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7a275567df
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pass metadata: added the output of parameters,
it's kinda dumb at the moment and needs parsing based on type but it's a start
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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d8b85e1247
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pass metadata: fixed some of the output formatting
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2022-04-08 08:05:15 +02:00 |
Aki Van Ness
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f6bb238051
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pass metadata: initial commit of the metadata pass for exporting design metadata for yosys assisted tooling
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2022-04-08 08:05:15 +02:00 |
Iris Johnson
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ccc6060f52
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Makefile: properly conditionalize features requiring compression.
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2022-04-07 20:07:44 -05:00 |