mirror of https://github.com/YosysHQ/yosys.git
pass jny: added connection output
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parent
167206f2f5
commit
58e2870261
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@ -137,6 +137,63 @@ struct JnyWriter
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f << "}\n";
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}
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void write_sigspec(const RTLIL::SigSpec& sig, uint16_t indent_level = 0) {
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const auto _indent = gen_indent(indent_level);
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f << _indent << " {\n";
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f << _indent << " \"width\": \"" << sig.size() << "\",\n";
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f << _indent << " \"type\": \"";
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if (sig.is_wire()) {
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f << "wire";
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} else if (sig.is_chunk()) {
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f << "chunk";
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} else if (sig.is_bit()) {
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f << "bit";
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} else {
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f << "unknown";
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}
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f << "\",\n";
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f << _indent << " \"const\": ";
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if (sig.has_const()) {
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f << "true";
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} else {
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f << "false";
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}
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f << "\n";
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f << _indent << " }";
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}
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void write_mod_conn(const std::pair<RTLIL::SigSpec, RTLIL::SigSpec>& conn, uint16_t indent_level = 0) {
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const auto _indent = gen_indent(indent_level);
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f << _indent << " {\n";
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f << _indent << " \"signals\": [\n";
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write_sigspec(conn.first, indent_level + 2);
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f << ",\n";
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write_sigspec(conn.second, indent_level + 2);
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f << "\n";
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f << _indent << " ]\n";
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f << _indent << " }";
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}
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void write_cell_conn(const std::pair<RTLIL::IdString, RTLIL::SigSpec>& sig, uint16_t indent_level = 0) {
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const auto _indent = gen_indent(indent_level);
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f << _indent << " {\n";
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f << _indent << " \"name\": " << get_string(RTLIL::unescape_id(sig.first)) << ",\n";
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f << _indent << " \"signals\": [\n";
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write_sigspec(sig.second, indent_level + 2);
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f << "\n";
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f << _indent << " ]\n";
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f << _indent << " }";
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}
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void write_module(Module* mod, uint16_t indent_level = 0) {
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log_assert(mod != nullptr);
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@ -159,12 +216,22 @@ struct JnyWriter
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f << _indent << " ]";
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if (_include_connections) {
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f << _indent << ",\n \"connections\": [\n";
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f << ",\n" << _indent << " \"connections\": [\n";
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bool first_conn{true};
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for (const auto& conn : mod->connections()) {
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if (!first_conn)
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f << ",\n";
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write_mod_conn(conn, indent_level + 2);
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first_conn = false;
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}
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f << _indent << " ]";
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}
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if (_include_attributes) {
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f << _indent << ",\n \"attributes\": {\n";
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f << ",\n" << _indent << " \"attributes\": {\n";
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write_prams(mod->attributes, indent_level + 2);
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@ -271,8 +338,25 @@ struct JnyWriter
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f << _indent << " {\n";
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f << stringf(" %s\"name\": %s", _indent.c_str(), get_string(RTLIL::unescape_id(cell->name)).c_str());
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if (_include_connections) {
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f << ",\n" << _indent << " \"connections\": [\n";
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bool first_conn{true};
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for (const auto& conn : cell->connections()) {
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if (!first_conn)
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f << ",\n";
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write_cell_conn(conn, indent_level + 2);
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first_conn = false;
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}
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f << "\n";
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f << _indent << " ]";
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}
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if (_include_attributes) {
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f << _indent << ",\n \"attributes\": {\n";
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f << ",\n" << _indent << " \"attributes\": {\n";
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write_prams(cell->attributes, indent_level + 2);
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@ -281,7 +365,7 @@ struct JnyWriter
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}
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if (_include_properties) {
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f << _indent << ",\n \"parameters\": {\n";
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f << ",\n" << _indent << " \"parameters\": {\n";
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write_prams(cell->parameters, indent_level + 2);
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