Eddie Hung
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de3e5fcdc6
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ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
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2020-02-28 12:33:55 -08:00 |
Claire Wolf
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ab8826ae36
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Merge pull request #1709 from rqou/coolrunner2_counter
Improve CoolRunner-II optimization by using extract_counter pass
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2020-02-27 19:05:56 +01:00 |
Miodrag Milanović
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036c46de1e
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Merge pull request #1705 from YosysHQ/logger_pass
Logger pass
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2020-02-26 13:32:49 +01:00 |
Miodrag Milanovic
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48eed2860c
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Fix line endings
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2020-02-23 10:05:21 +01:00 |
Miodrag Milanovic
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010d651450
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Update explanation for expect-no-warnings
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2020-02-22 10:53:23 +01:00 |
Miodrag Milanovic
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596bb2d443
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Check other regex parameters
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2020-02-22 10:31:56 +01:00 |
Alberto Gonzalez
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750e7a9a54
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Closes #1714. Fix make failure when NDEBUG=1.
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2020-02-22 06:29:11 +00:00 |
Eddie Hung
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760096e8d2
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Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
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2020-02-21 09:15:17 -08:00 |
Miodrag Milanovic
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419e67c170
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check for regex errors
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2020-02-20 11:41:37 +01:00 |
Eddie Hung
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1d401a7991
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clean: ignore specify-s inside cells when determining whether to keep
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2020-02-19 10:45:10 -08:00 |
Miodrag Milanovic
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5641b0248f
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Option to expect no warnings
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2020-02-17 15:36:06 +01:00 |
R. Ou
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fec7dc5c9e
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extract_counter: Implement extracting up counters
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2020-02-17 03:08:52 -08:00 |
R. Ou
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940bab6841
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extract_counter: Add support for inverted clock enable
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2020-02-17 03:08:52 -08:00 |
R. Ou
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5fc180ed2d
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extract_counter: Fix clock enable
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2020-02-17 03:08:52 -08:00 |
R. Ou
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12fa4a3121
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extract_counter: Fix outputting count to module port
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2020-02-17 03:08:52 -08:00 |
R. Ou
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508f1ff6a1
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extract_counter: Allow forbidding async reset
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2020-02-17 03:08:52 -08:00 |
R. Ou
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7b922c0d89
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extract_counter: Refactor out extraction settings into struct
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2020-02-17 03:08:52 -08:00 |
Tim 'mithro' Ansell
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b9dfdbbfee
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show: Add -nobg argument.
Makes yosys wait for the viewer command to finish before continuing.
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2020-02-15 14:03:16 +01:00 |
Eddie Hung
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f9f86fd758
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Revert "abc9: fix abc9_arrival for flops"
This reverts commit f7c0dbecee .
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2020-02-14 16:08:04 -08:00 |
Miodrag Milanovic
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31b7a9c312
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Add expect option to logger command
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2020-02-14 12:21:16 +01:00 |
Eddie Hung
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0cf7598cd6
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Merge pull request #1700 from YosysHQ/eddie/abc9_fixes
Use (* abc9_init *) attribute, fix use of abc9_arrival for flops
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2020-02-13 17:32:54 -08:00 |
Eddie Hung
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3d2a2e8799
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iopadmap: fixes as suggested by @mwkmwkmwk
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2020-02-13 14:57:06 -08:00 |
Eddie Hung
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f7c0dbecee
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abc9: fix abc9_arrival for flops
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2020-02-13 12:34:09 -08:00 |
Eddie Hung
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00d41905df
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abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr
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2020-02-13 12:33:58 -08:00 |
Eddie Hung
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ebb11bcea4
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iopadmap: move \init attributes from outpad output to its input
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2020-02-13 12:05:14 -08:00 |
Miodrag Milanovic
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0ba2a2b1fa
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Add new logger pass
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2020-02-13 13:35:29 +01:00 |
Eddie Hung
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c244b27b6d
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abc9: cleanup
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2020-02-10 10:17:23 -08:00 |
Eddie Hung
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e6bb7b0782
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Fix misc.abc9.abc9_abc9_luts
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2020-02-07 08:27:45 -08:00 |
Eddie Hung
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505557e93e
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Merge pull request #1576 from YosysHQ/eddie/opt_merge_init
opt_merge: discard \init of '$' cells with 'Q' port when merging
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2020-02-05 14:56:26 -08:00 |
Eddie Hung
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0b308c6835
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abc9_ops: -reintegrate to use derived_type for box_ports
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2020-02-05 14:46:48 -08:00 |
Eddie Hung
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5ebdc0f8e0
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Merge pull request #1638 from YosysHQ/eddie/fix1631
clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_*
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2020-02-05 19:31:18 +01:00 |
Eddie Hung
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0671ae7d79
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Merge pull request #1661 from YosysHQ/eddie/abc9_required
abc9: add support for required times
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2020-02-05 18:59:40 +01:00 |
Marcelina Kościelnicka
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34d2fbd2f9
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Add opt_lut_ins pass. (#1673)
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2020-02-03 14:57:17 +01:00 |
David Shah
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4bfd2ef4f3
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sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
David Shah
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7e741714df
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hierarchy: Correct handling of wildcard port connections with default values
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
David Shah
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5df591c023
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hierarchy: Resolve SV wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-02 16:12:33 +00:00 |
David Shah
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1055b6b1dd
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Merge pull request #1657 from YosysHQ/dave/xilinx-dsp-multonly
synth_xilinx: add -dsp-multonly
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2020-02-02 14:53:32 +00:00 |
David Shah
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65716c9982
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xilinx_dsp: Add multonly scratchpad var to bypass
Signed-off-by: David Shah <dave@ds0.me>
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2020-02-01 15:30:43 +00:00 |
Gabriel Somlo
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8106c3d31b
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abc9: restore ability to use ABCEXTERNAL
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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2020-01-30 15:12:43 -05:00 |
Claire Wolf
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1679682fa3
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Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
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2020-01-29 17:01:24 +01:00 |
Claire Wolf
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4d0118d0c1
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Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
opt_reduce: Call check() per run rather than per optimised cell
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2020-01-29 15:27:11 +01:00 |
Eddie Hung
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a855f23f22
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Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
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2020-01-28 12:46:18 -08:00 |
Eddie Hung
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7939727d14
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Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
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2020-01-28 11:55:51 -08:00 |
Claire Wolf
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4ddaa70fd6
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Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
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2020-01-28 17:40:28 +01:00 |
N. Engelhardt
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086c133ea5
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Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
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2020-01-28 17:24:54 +01:00 |
David Shah
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6fd9cae5ca
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opt_reduce: Call check() per run rather than per optimised cell
Signed-off-by: David Shah <dave@ds0.me>
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2020-01-28 09:42:01 +00:00 |
Pepijn de Vos
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409e532433
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redirect fuser stderr to /dev/null
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2020-01-28 10:02:41 +01:00 |
Eddie Hung
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21ce1b37fb
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abc9_ops: -check for negative arrival/required times
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2020-01-27 14:22:46 -08:00 |
Eddie Hung
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e18aeda7ed
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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
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2020-01-27 14:02:13 -08:00 |
Eddie Hung
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48f3f5213e
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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
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2020-01-27 13:29:15 -08:00 |