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6428 Commits

Author SHA1 Message Date
David Shah 5545cd3c10
Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 
ecp5: Make cells_sim.v consistent with nextpnr
 2019-08-07 15:35:29 +01:00
Clifford Wolf 9260e97aa2 Automatically prune init attributes in verific front-end, fixes #1237 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 15:31:49 +02:00
David Shah a36fd8582e ecp5: Make cells_sim.v consistent with nextpnr 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:19:31 +01:00
Clifford Wolf e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add 
wreduce/opt_expr: improve width reduction for $add and $sub cells
 2019-08-07 14:27:35 +02:00
Clifford Wolf 48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
Clifford Wolf 4c49ddf36a
Merge pull request #1249 from mmicko/anlogic_fix 
anlogic : Fix alu mapping
 2019-08-07 12:30:52 +02:00
Clifford Wolf 679bc6507f
Merge pull request #1252 from YosysHQ/clifford/fix1231 
Fix handling of functions/tasks without top-level begin-end block
 2019-08-07 12:14:54 +02:00
Clifford Wolf c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check 
Be less aggressive with running design->check()
 2019-08-07 12:14:41 +02:00
Clifford Wolf f1ac998bb4
Merge pull request #1257 from YosysHQ/clifford/cellcosts 
Redesign of cell cost API
 2019-08-07 12:13:50 +02:00
David Shah 607c7fa7e1 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 10:56:32 +01:00
David Shah dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix 
Improved JSON attr/param encoding
 2019-08-07 10:40:38 +01:00
Clifford Wolf 338f6765eb Tweak default gate costs, cleanup "stat -tech cmos" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 10:25:51 +02:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Eddie Hung 234fcf1724 Fix typos 2019-08-06 19:07:45 -07:00
Eddie Hung e5be9ff871 Fix spacing 2019-08-06 16:47:55 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung a6bc9265fb RTLIL::S{0,1} -> State::S{0,1} 2019-08-06 16:23:37 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Eddie Hung 43081337fa Cleanup opt_expr.cc 2019-08-06 16:04:21 -07:00
Eddie Hung 2d1b517b01 Add signed opt_expr tests 2019-08-06 15:40:30 -07:00
Eddie Hung 769c750c22 Add signed test 2019-08-06 15:38:43 -07:00
Eddie Hung bfc7164af7 Move LSB-trimming functionality from wreduce to opt_expr 2019-08-06 15:25:50 -07:00
Eddie Hung 84f52aee0d Add SigSpec::extract_end() convenience function 2019-08-06 15:25:11 -07:00
Eddie Hung 0b56be8c56 Restore original SigSpec::extract() 2019-08-06 15:24:55 -07:00
Eddie Hung 51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah 8110fb9266
Merge pull request #1232 from YosysHQ/dave/write_gzip 
Add support for writing gzip-compressed files
 2019-08-06 19:05:35 +01:00
Clifford Wolf 95a6582f34 Be less aggressive with running design->check() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 19:21:37 +02:00
David Shah 3a3da678ad Add test for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
David Shah 27360ceda6 Add support for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00
Clifford Wolf a4b59de5d4
Merge pull request #1251 from YosysHQ/clifford/nmux 
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
 2019-08-06 15:18:18 +02:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Miodrag Milanovic 837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
whitequark 44a9dcbbbf
Merge pull request #1242 from jfng/fix-proc_prune-partial 
proc_prune: Promote partially redundant assignments.
 2019-08-03 07:08:41 +00:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Clifford Wolf f4ae6afc22
Merge pull request #1239 from mmicko/mingw_fix 
Fix formatting for msys2 mingw build
 2019-08-02 16:37:57 +02:00
Eddie Hung e8a2d10982
Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_map 
xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
 2019-08-01 09:38:55 -07:00
Miodrag Milanovic 7a65ed19a5 Fix linking issue for new mxe and pthread 2019-08-01 17:30:02 +02:00
Miodrag Milanovic 3f633690ae Fix yosys linking for mxe 2019-08-01 17:28:07 +02:00
Miodrag Milanovic f767179c75 New mxe hacks needed to support 2ca237e 2019-08-01 17:28:07 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Jean-François Nguyen 320bf2fde5 proc_prune: Promote partially redundant assignments. 2019-08-01 13:09:55 +02:00
Clifford Wolf 292f03355a Update JSON front-end to process new attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:48:22 +02:00
Clifford Wolf 15fae357f6 Implement improved JSON attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:34:52 +02:00
Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
 2019-07-31 09:27:38 -07:00
Clifford Wolf acd8bc0a74
Merge pull request #1233 from YosysHQ/clifford/defer 
Call "read_verilog" with -defer from "read"
 2019-07-31 13:30:52 +02:00