riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,203 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

132 Commits

Author SHA1 Message Date
Miodrag Milanovic d8735b2913 Add to changelog 2020-02-17 15:08:35 +01:00
Rodrigo A. Melo 665a967d87
Merge branch 'master' into master 2020-02-03 11:07:51 -03:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Rodrigo Alejandro Melo 313a425bd5 Merge branch 'master' of https://github.com/YosysHQ/yosys 
Solved a conflict into the CHANGELOG

Signed-off-by: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
 2020-02-03 10:56:41 -03:00
David Shah 0488492ad2 Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:13:13 +00:00
Rodrigo Alejandro Melo 2774aae0f2 Removed a line jump into the CHANGELOG 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-02-01 22:56:01 -03:00
Rodrigo Alejandro Melo 7b3fe404ab $readmem[hb] file inclusion is now relative to the Verilog file 
Signed-off-by: Rodrigo Alejandro Melo <rodrigomelo9@gmail.com>
 2020-01-31 18:20:22 -03:00
Eddie Hung 345e98f871 Add 'abc9 -dff' to CHANGELOG 2020-01-02 12:42:28 -08:00
Eddie Hung ece423415c Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md 2019-12-30 14:24:58 -08:00
Eddie Hung f52c6efd9d Add "scratchpad" to CHANGELOG 2019-12-18 12:09:11 -08:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
David Shah b60f32c6ec Update CHANGELOG and README 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-22 12:46:19 +00:00
Clifford Wolf 45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Marcin Kościelnicki 4535f2c694 synth_xilinx: Support latches, remove used-up FF init values. 
Fixes #1387.
 2019-09-30 12:52:43 +02:00
Eddie Hung 3fb839e255 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-20 12:21:36 -07:00
Clifford Wolf c072e00a39 Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-20 10:28:20 +02:00
Eddie Hung b88f0f6450 Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
Eddie Hung 0020a18929 Add more entries 2019-09-19 12:00:39 -07:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung a1123b095c Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-12 12:11:11 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Eddie Hung feb3fa65a3 Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-11 00:01:31 -07:00
Eddie Hung 04153c5011 Update CHANGELOG 2019-09-10 16:14:26 -07:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Eddie Hung 1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung bd3773a17f Remove dupe in CHANGELOG, missing end quote 2019-08-26 10:44:23 -07:00
Clifford Wolf 8a4c6e6563 Merge tag 'yosys-0.9' 2019-08-26 11:14:22 +02:00
Eddie Hung cee30deef5 Mention shregmap -tech xilinx is superseded 2019-08-23 12:24:25 -07:00
Eddie Hung f4fd41d5d2 Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl 2019-08-23 11:35:06 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Clifford Wolf adb81ba386 Add pmgen slices and choices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:15:50 +02:00
Eddie Hung 7a9031c48e Add CHANGELOG entry 2019-08-22 11:22:53 -07:00
Eddie Hung 33960dd3d8
Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 
[WIP] synth xilinx renaming, as per #1184
 2019-08-20 12:55:26 -07:00
Eddie Hung d9fe4cccbf Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx 2019-08-20 11:57:52 -07:00
Clifford Wolf 1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Eddie Hung a29814ca3f Add 'opt_share' to CHANGELOG 2019-08-16 13:47:51 -07:00
Clifford Wolf 016036f247 Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-15 23:02:37 +02:00
Marcin Kościelnicki 49765ec19e minor review fixes 2019-08-13 18:05:49 +00:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung 9962e6fc1a Update CHANGELOG 2019-08-07 16:33:46 -07:00
David Shah 607c7fa7e1 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 10:56:32 +01:00
David Shah 27360ceda6 Add support for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
David Shah 82a2972068 Update CHANGELOG 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 16:45:51 +01:00