yosys

Commit Graph

Author	SHA1	Message	Date
whitequark	1719aa88ac	Extract ice40_unlut pass from ice40_opt. Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.	2018-12-05 16:30:24 +00:00
Clifford Wolf	6fe3d5a1cf	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
Clifford Wolf	0793f1b196	Added ice40_ffinit pass	2015-11-26 18:11:06 +01:00
Clifford Wolf	c475deec6c	Switched to Python 3	2015-08-22 09:59:33 +02:00
Clifford Wolf	9596fe74de	Another bugfix for ice40 and xilinx brams_init make rules	2015-08-16 21:39:34 +02:00
Clifford Wolf	aedcfd6fd3	Fixed Makefile rules for generated share files	2015-08-16 21:15:07 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Clifford Wolf	61512b6f41	Verific build fixes	2015-05-17 08:19:52 +02:00
Clifford Wolf	8d4a675f91	Added iCE40 const folding support for SB_CARRY	2015-04-27 08:38:14 +02:00
Clifford Wolf	752851954b	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Clifford Wolf	d6f7698f59	Added ice40 bram support	2015-04-24 00:06:50 +02:00
Clifford Wolf	f78fa718be	Added ice40 SB_CARRY support	2015-04-18 09:33:08 +02:00
Clifford Wolf	661b647559	Added mapping of synchronous set/reset to iCE40 flow	2015-04-17 11:54:25 +02:00
Clifford Wolf	42d5d94a5d	Added very first version of "synth_ice40"	2015-03-05 20:37:55 +01:00

14 Commits