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744 Commits

Author SHA1 Message Date
Eddie Hung 8182cb9d91 Fix omode which inserts an output if none exists (otherwise abc9 breaks) 2019-08-20 21:30:16 -07:00
Eddie Hung 4d123b7638 Revert "Only xaig if GetSize(output_bits) > 0" 
This reverts commit 7b646101e9.
 2019-08-20 21:22:38 -07:00
Eddie Hung 7b646101e9 Only xaig if GetSize(output_bits) > 0 2019-08-20 20:57:13 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung 1b5d2de1d4 Do not sigmap! 2019-08-20 15:23:26 -07:00
Eddie Hung c00d72cdb3 Minor refactor 2019-08-20 14:47:58 -07:00
Eddie Hung 45d4b33f0c Output i/o/h extensions even if no boxes or flops 2019-08-19 13:17:31 -07:00
Eddie Hung 91687d3fea Add (* abc_arrival *) attribute 2019-08-19 12:33:24 -07:00
Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung 10c69f71e9 Use %d 2019-08-19 09:16:20 -07:00
Eddie Hung 24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung 4fe307f1bc Compute abc_scc_break and move CI/CO outside of each abc9 2019-08-16 15:41:17 -07:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf 05c46a31dc
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell 
FIRRTL error on unsupported cell
 2019-08-10 09:47:10 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Jim Lawson 5e8a98c8fd Merge branch 'master' into firrtl_err_on_unsupported_cell 
# Conflicts:
#	backends/firrtl/firrtl.cc
 2019-08-07 10:14:45 -07:00
Eddie Hung 3090da2d98 Run "clean -purge" on holes_module in its own design 2019-08-07 09:54:27 -07:00
Clifford Wolf 48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor 
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
 2019-08-07 12:31:32 +02:00
David Shah dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix 
Improved JSON attr/param encoding
 2019-08-07 10:40:38 +01:00
Eddie Hung e38f40af5b Use IdString::begins_with() 2019-08-06 16:42:25 -07:00
Eddie Hung a6bc9265fb RTLIL::S{0,1} -> State::S{0,1} 2019-08-06 16:23:37 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Clifford Wolf 15fae357f6 Implement improved JSON attr/param encoding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-01 12:34:52 +02:00
Jim Lawson 3b8c917025 Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. 
Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
 2019-07-31 09:27:38 -07:00
Miodrag Milanovic 35d28de478 Visual Studio build fix 2019-07-31 09:10:24 +02:00
Jim Lawson 7e298084e4 Call log_error() instead of log_warning() on unsupported cell type in FIRRTL backend. 2019-07-24 13:33:16 -07:00
Clifford Wolf 927f0caa9d
Merge pull request #1203 from whitequark/write_verilog-zero-width-values 
write_verilog: dump zero width constants correctly
 2019-07-18 15:31:27 +02:00
Clifford Wolf 56c00e871f Remove old $pmux_safe code from write_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-17 11:49:04 +02:00
whitequark 4ff44d85a5 write_verilog: dump zero width constants correctly. 
Before this commit, zero width constants were dumped as "" (empty
string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty
string is equivalent to "\0", and is 8 bits wide, so that's wrong.

After this commit, a replication operation with a count of zero is
used instead, which is explicitly permitted per 1364-2005 5.1.14,
and is defined to have size zero. (Its operand has to have a non-zero
size for it to be legal, though.)

Fixes #948 (again).
 2019-07-16 21:00:09 +00:00
N. Engelhardt ab4b9e8db4 smt: handle failure of setrlimit syscall 2019-07-15 23:33:18 +08:00
Clifford Wolf 9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark 
write_verilog: write RTLIL::Sa aka - as Verilog ?
 2019-07-11 07:25:52 +02:00
Eddie Hung 375fcbe511 abc_flop to also get topologically sorted 2019-07-10 20:26:09 -07:00
Eddie Hung ea6ffea2cd Fix clk_pol for FD*_1 2019-07-10 20:10:20 -07:00
Eddie Hung e603d719d6 Fix spacing 2019-07-10 19:04:22 -07:00
Eddie Hung 4a995c5d80 Change how to specify flops to ABC again 2019-07-10 17:54:56 -07:00
Eddie Hung a092c48f03 Use split_tokens() 2019-07-10 17:34:51 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
Clifford Wolf 6dd33be7ce
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 
write_verilog: fix placement of case attributes
 2019-07-09 22:51:25 +02:00
whitequark 37bb6b5e96 write_verilog: fix placement of case attributes. NFC. 2019-07-09 19:14:03 +00:00
whitequark 6a29e1f5b7 write_verilog: write RTLIL::Sa aka - as Verilog ?. 
Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.
 2019-07-09 18:35:49 +00:00
Eddie Hung 00d8a9dce2
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore 
Rename __builtin_bswap32 -> bswap32
 2019-07-09 10:22:57 -07:00
Eddie Hung 5a0f2e43c7 Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
whitequark 628437b01c verilog_backend: dump attributes on SwitchRule. 
This appears to be an omission.
 2019-07-08 15:11:29 +00:00