Clifford Wolf
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7b62bbeee8
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Added more documentation fixmes for nontrivial register cells
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2014-12-08 10:56:43 +01:00 |
Clifford Wolf
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af0c8873bb
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Added $lcu cell type
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2014-09-08 13:31:04 +02:00 |
Clifford Wolf
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8927aa6148
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Removed $bu0 cell type
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2014-09-04 02:07:52 +02:00 |
Clifford Wolf
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4724d94fbc
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Added $alu cell type
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2014-08-30 18:59:05 +02:00 |
Clifford Wolf
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47c2637a96
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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2014-08-16 18:29:39 +02:00 |
Clifford Wolf
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f092b50148
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Renamed $_INV_ cell type to $_NOT_
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2014-08-15 14:11:40 +02:00 |
Clifford Wolf
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bf486002d9
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Removed old doc references to $safe_pmux
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2014-08-15 14:04:35 +02:00 |
Clifford Wolf
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73e0e13d2f
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Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
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2014-07-16 11:38:02 +02:00 |
Clifford Wolf
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fc3b3c4ec3
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Added $slice and $concat cell types
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2014-02-07 17:44:57 +01:00 |
Clifford Wolf
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a6750b3753
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Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
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1e67099b77
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Added $assert cell
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2014-01-19 14:03:40 +01:00 |
Clifford Wolf
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fb2bf934dc
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Added correct handling of $memwr priority
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2014-01-03 00:22:17 +01:00 |
Clifford Wolf
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fe8ec32a1c
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Added new cell types to manual
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2013-12-28 12:10:32 +01:00 |
Clifford Wolf
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288ba9618a
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Moved common techlib files to techlibs/common
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2013-09-15 11:52:57 +02:00 |
Clifford Wolf
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61ed6b32d1
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Added Yosys Manual
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2013-07-20 15:19:12 +02:00 |