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Added more documentation fixmes for nontrivial register cells

This commit is contained in:
Clifford Wolf 2014-12-08 10:56:43 +01:00
parent f1764b4fe9
commit 7b62bbeee8
1 changed files with 9 additions and 1 deletions
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10
manual/CHAPTER_CellLib.tex
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@ -357,7 +357,7 @@ Add a brief description of the {\tt \$fsm} cell type.
For gate level logic networks, fixed function single bit cells are used that do
not provide any parameters.
Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
source tree.
\begin{table}[t]
@ -428,6 +428,14 @@ Add information about {\tt \$slice} and {\tt \$concat} cells.
Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
\end{fixme}
\begin{fixme}
Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dlatchsr} cells.
\end{fixme}
\begin{fixme}
Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
\end{fixme}
\begin{fixme}
Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
\end{fixme}