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6002 Commits

Author SHA1 Message Date
Clifford Wolf d206eca03b Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-02 11:36:26 +02:00
Eddie Hung 6282a67332 Space 2019-07-01 11:59:10 -07:00
Eddie Hung 9018f29d54 Move CHANGELOG entry from yosys-0.8 to 0.9 2019-07-01 09:46:56 -07:00
Eddie Hung dda2ec3cc5 Merge branch 'master' into eddie/script_from_wire 2019-07-01 09:46:32 -07:00
Eddie Hung 0067dc44f3 Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG 2019-07-01 09:44:53 -07:00
Eddie Hung 7be8551c8d Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-01 09:43:33 -07:00
Eddie Hung 04459cb30a Comment out invalid syntax 2019-06-30 11:48:01 -07:00
Eddie Hung 85f1c2dcbe Cleanup SRL inference/make more consistent 2019-06-29 21:42:20 -07:00
Eddie Hung dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung c5563b67c8
Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup 
Make abc9 pass aware of optional ABCEXTERNAL override
 2019-06-28 15:02:50 -07:00
Eddie Hung fd2fb4f0f0 Merge branch 'master' into eddie/script_from_wire 2019-06-28 14:56:34 -07:00
Eddie Hung 0ec7c09756 autotest.sh to define _AUTOTB when test_autotb 2019-06-28 14:56:22 -07:00
Eddie Hung 64f6b0c747 Try command in another module 2019-06-28 13:41:32 -07:00
Eddie Hung 4e1a4927e2 Add to CHANGELOG 2019-06-28 13:39:06 -07:00
Eddie Hung 06971385fa Support ability for "script -select" to take commands from wires 2019-06-28 13:36:33 -07:00
Eddie Hung 2c6aaef3db Add test 2019-06-28 13:32:09 -07:00
Eddie Hung b3f162e94e Replace log_assert() with meaningful log_error() 2019-06-28 12:54:44 -07:00
Eddie Hung 728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung b5f1bd0df1 Add missing CHANGELOG entries 2019-06-28 11:16:15 -07:00
Eddie Hung 4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Eddie Hung 38d8806bd7 Add generic __builtin_bswap32 function 2019-06-28 09:59:47 -07:00
Eddie Hung 524af21317 Also fix write_aiger for UB 2019-06-28 09:55:07 -07:00
Eddie Hung 36e2eb06bb Fix more potential for undefined behaviour due to container invalidation 2019-06-28 09:51:43 -07:00
Eddie Hung 03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung 3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung 0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00
Clifford Wolf 74945dd738
Merge pull request #1146 from gsomlo/gls-test-abc-ext 
tests: use optional ABCEXTERNAL when specified
 2019-06-28 10:30:31 +02:00
Clifford Wolf af74409749 Improve specify dummy parser, fixes #1144 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-28 10:21:16 +02:00
Clifford Wolf 1c7ce251f3
Merge pull request #1046 from bogdanvuk/master 
Optimizing DFFs whose initial value prevents their value from changing
 2019-06-28 08:30:18 +02:00
Gabriel L. Somlo 6f1c137989 tests: use optional ABCEXTERNAL when specified 
Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation
of yosys-abc, which fails if ABCEXTERNAL was specified during the
build. Allow tests to utilize an optional, externally specified
abc binary.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-27 23:00:13 -04:00
Eddie Hung 00f63d82ce Reduce diff with upstream 2019-06-27 16:13:22 -07:00
Eddie Hung af8a5ae5fe Extraneous newline 2019-06-27 16:12:20 -07:00
Eddie Hung 4daa746797 Remove noise from ice40/cells_sim.v 2019-06-27 16:11:39 -07:00
Eddie Hung 9398921af1 Refactor for one "abc_carry" attribute on module 2019-06-27 16:07:14 -07:00
Eddie Hung 550760cc72 Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-27 15:30:00 -07:00
Eddie Hung a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung 312c03e4ca Remove redundant doc 2019-06-27 15:28:55 -07:00
Eddie Hung 137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung 6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Eddie Hung fb30fcb7c5 Undo iterator based Module::remove() for cells, as containers will not 
invalidate
 2019-06-27 15:03:21 -07:00
Bogdan Vukobratovic 3225bfb984 Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too 2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic 35fa7b3057 Fix memory leak when one of multiple DFF cells is removed in opt_rmdff 
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
 2019-06-27 22:02:12 +02:00
Eddie Hung 9a371cfba9 Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 12:53:23 -07:00
Eddie Hung c4c39e9814
Merge pull request #1139 from YosysHQ/dave/check-sim-iverilog 
tests: Check that Icarus can parse arch sim models
 2019-06-27 12:31:15 -07:00
Eddie Hung 440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung eab8384ec7 Grr 2019-06-27 11:53:42 -07:00