riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
5,390 Commits 92 Branches 49 Tags 39 MiB
Commit Graph

5390 Commits

Author SHA1 Message Date
Clifford Wolf bacca57537 Fix smtbmc.py handling of zero appended steps 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf 6ad5d036c5 Add "mutate" command DB reduce functionality 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf 76c9c350e7 Add hashlib "<container>::element(int n)" methods 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf 8e6b69d7bb Add "mutate -mode inv", various other mutate improvements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf ea8ee24140 Add basic "mutate -list N" framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 22:04:42 +01:00
Clifford Wolf c4575103af
Merge pull request #874 from YosysHQ/clifford/andopt 
Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327
 2019-03-14 21:22:16 +01:00
Clifford Wolf f806b95ed6 Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 20:52:00 +01:00
Clifford Wolf 44a44a06ed
Merge pull request #872 from YosysHQ/clifford/pmuxfix 
Improve handling of "full_case" attributes
 2019-03-14 18:42:45 +01:00
Clifford Wolf 17caaa3fa8 Improve handling of "full_case" attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:51:21 +01:00
Clifford Wolf 04e920337b Fix a syntax bug in ilang backend related to process case statements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:50:20 +01:00
Eddie Hung e7ef7fa443 Reverse bits in INIT parameter for Xilinx, since MSB is shifted first 2019-03-14 09:38:42 -07:00
Eddie Hung af5706c2a3 Misspell 2019-03-14 09:06:56 -07:00
Eddie Hung 8af9979aab Revert "Add shregmap -init_msb_first and use in synth_xilinx" 
This reverts commit 26ecbc1aee.
 2019-03-14 09:01:48 -07:00
Eddie Hung f1a8e8a480 Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-14 08:59:19 -07:00
Clifford Wolf 53b28b3f01
Merge pull request #869 from cr1901/win-shell 
Install launcher executable when running yosys-smtbmc on Windows.
 2019-03-14 16:43:23 +01:00
Eddie Hung 26ecbc1aee Add shregmap -init_msb_first and use in synth_xilinx 2019-03-14 08:10:02 -07:00
Eddie Hung 79b4a275ce Fix cells_map for SRL 2019-03-14 08:09:48 -07:00
Eddie Hung edca2f1163 Move shregmap until after first techmap 2019-03-13 17:13:52 -07:00
Eddie Hung 24f129ddfb Refactor $__SHREG__ in cells_map.v 2019-03-13 16:17:54 -07:00
William D. Jones ff15cf9b1f Install launcher executable when running yosys-smtbmc on Windows. 
Signed-off-by: William D. Jones <thor0505@comcast.net>
 2019-03-13 13:49:16 -04:00
Clifford Wolf f0b2d8e467
Merge pull request #868 from YosysHQ/clifford/fixmem 
Various mem2reg-related improvements in handling of memories
 2019-03-13 13:40:30 +01:00
Clifford Wolf 1cd04a6838 Fix a bug in handling quotes in multi-cmd lines in Yosys scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 21:15:11 +01:00
Clifford Wolf ac10f72e49
Merge pull request #866 from YosysHQ/clifford/idstuff 
Improve determinism of IdString DB for similar scripts
 2019-03-12 20:27:36 +01:00
Clifford Wolf 9284cf92b8 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:14:18 +01:00
Clifford Wolf d25a0c8ade Improve handling of memories used in mem index expressions on LHS of an assignment 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:12:02 +01:00
Clifford Wolf a4ddc569b4 Remove outdated "blocking assignment to memory" warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:10:55 +01:00
Clifford Wolf ab5b50ae3c Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:09:47 +01:00
Clifford Wolf 20c6a8c9b0 Improve determinism of IdString DB for similar scripts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 20:12:28 +01:00
Eddie Hung ef48b62cb1
Merge pull request #864 from YosysHQ/svalabelfix 
Fix handling of cases that look like sva labels, fixes #862
 2019-03-11 11:58:07 -07:00
Clifford Wolf d9bb5f3637 Add ENABLE_GLOB Makefile switch 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-11 01:08:36 -07:00
Clifford Wolf b02d9c2634 Fix handling of cases that look like sva labels, fixes #862 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-10 16:27:18 -07:00
Clifford Wolf ff4c2a14ae Fix typo in ice40_braminit help msg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:24:55 -08:00
Clifford Wolf 2ace1b0041
Merge pull request #859 from smunaut/ice40_braminit 
iCE40 BRAM primitives init from file
 2019-03-09 13:24:10 -08:00
Clifford Wolf 94f995ee37 Fix signed $shift/$shiftx handling in write_smt2 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 13:19:41 -08:00
Clifford Wolf 399ab16315 Add $dffsr support to async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-09 11:52:00 -08:00
Clifford Wolf cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels 
Add support for using SVA labels in yosys-smtbmc console output
 2019-03-09 11:14:57 -08:00
Clifford Wolf 7504d4d345
Merge pull request #861 from YosysHQ/verific_chparam 
Add -chparam option to verific command
 2019-03-08 23:02:56 -08:00
Clifford Wolf e7a34d342e Also add support for labels on sva module items, fixes #699 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-08 22:55:09 -08:00
Eddie Hung ee013fba54 Update help message for -chparam 2019-03-09 01:56:16 +00:00
Eddie Hung 2aa3903757 Add -chparam option to verific command 2019-03-09 01:54:01 +00:00
Eddie Hung 1dc060f32e Fix spelling 2019-03-09 00:43:50 +00:00
Clifford Wolf e9b34ad5c0 Merge branch 'master' of github.com:YosysHQ/yosys 2019-03-07 22:44:50 -08:00
Clifford Wolf a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 22:44:37 -08:00
Sylvain Munaut 5b6f591033 ice40: Run ice40_braminit pass by default 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Sylvain Munaut e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file 
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-03-08 00:15:46 +01:00
Clifford Wolf df0598f455
Merge pull request #856 from kprasadvnsi/master 
examples/anlogic/ now also output the SVF file.
 2019-03-07 11:34:12 -08:00
Clifford Wolf 5dfc7becca Use SVA label in smt export if available 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:31:46 -08:00
Clifford Wolf 22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf cda37830b0 Add hack for handling SVA labels via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 10:52:44 -08:00
Clifford Wolf 350dfd3745 Add link to SF2 / igloo2 macro library guide 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 09:08:26 -08:00