Commit Graph

5390 Commits

Author SHA1 Message Date
Benedikt Tutzer 0774a500d4 Added support for changing Yosys namespace 2019-04-03 12:21:21 +02:00
Benedikt Tutzer 539a7f3fbc Added cell_stats example 2019-04-03 11:24:50 +02:00
Benedikt Tutzer d287596be3 Added dependencies to README and travis configuration 2019-04-03 11:18:34 +02:00
Benedikt Tutzer adfd8d463d Autodetect highest installed python version 2019-04-03 11:17:50 +02:00
Clifford Wolf 721fa1cbd8
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
2019-04-03 10:00:18 +02:00
Clifford Wolf 3f6554d698
Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
2019-04-03 09:59:11 +02:00
David Shah 6acbc016f4 memory_bram: Consider read enable for address expansion register
Signed-off-by: David Shah <dave@ds0.me>
2019-04-02 19:47:50 +01:00
Miodrag Milanovic df92e9bdc2 Make nobram false by default for gowin 2019-04-02 19:21:01 +02:00
Eddie Hung aaa2690a56
Merge pull request #895 from YosysHQ/pmux2shiftx
RFC: Add a pmux-to-shiftx optimisation to proc_mux
2019-04-02 00:16:14 -07:00
Jim Lawson 73b87e7807 Refine memory support to deal with general Verilog memory definitions. 2019-04-01 15:02:12 -07:00
Jim Lawson b8dfda8767 Merge remote-tracking branch 'upstream/master' 2019-04-01 11:09:12 -07:00
Benedikt Tutzer 2586e09118 Removed generation of commented-out code 2019-04-01 15:05:30 +02:00
Benedikt Tutzer 7472c52686 Use addition assignment operator 2019-04-01 13:39:38 +02:00
Benedikt Tutzer 072c939380 Fixed identation 2019-04-01 13:36:01 +02:00
Clifford Wolf 22035c20ff
Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
2019-03-30 00:09:42 +01:00
Clifford Wolf 584d2030bf Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-29 16:32:44 +01:00
Benedikt Tutzer 03d1606b42 Merge remote-tracking branch 'origin/master' into feature/python_bindings 2019-03-28 12:16:39 +01:00
Clifford Wolf 32bd0f22ec
Merge pull request #901 from trcwm/libertyfixes
Libertyfixes: accept superfluous ; at end of group.
2019-03-28 09:32:05 +01:00
Clifford Wolf 662429cc49
Merge pull request #903 from YosysHQ/bram_reset_transp
memory_bram: Reset make_transp when growing read ports
2019-03-28 09:30:48 +01:00
David Shah 60594ad40c memory_bram: Reset make_transp when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
2019-03-27 17:19:14 +00:00
Niels Moseley 263ab60b43 Liberty file parser now accepts superfluous ; 2019-03-27 15:17:58 +01:00
Niels Moseley ee130f67cd Liberty file parser now accepts superfluous ; 2019-03-27 15:16:19 +01:00
Niels Moseley 487cb45b87 Liberty file parser now accepts superfluous ; 2019-03-27 15:15:53 +01:00
Clifford Wolf 7682629b79 Add "read -verific" and "read -noverific"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 14:03:35 +01:00
Clifford Wolf 2c7fe42ad1 Add "rename -output"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:47:42 +01:00
Clifford Wolf d351b7cb99 Improve "rename" help message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-27 13:33:26 +01:00
Clifford Wolf 38b3fbd3f0 Add "cutpoint -undef"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 16:01:14 +01:00
Clifford Wolf d0b9b1bece Add "hdlname" attribute
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:52:48 +01:00
Clifford Wolf c863796e9f Fix "verific -extnets" for more complex situations
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:17:46 +01:00
Eddie Hung f9fb05cf66 synth_xilinx to use shregmap with -minlen 3 2019-03-25 13:18:55 -07:00
Eddie Hung 6b90d3cf6c Merge remote-tracking branch 'origin/master' into xc7srl 2019-03-25 13:17:22 -07:00
Clifford Wolf ddc1a4488e Add "cutpoint" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-25 19:49:00 +01:00
Eddie Hung b7a3d35c6b Create one $shiftx per bit in width 2019-03-25 11:16:56 -07:00
Clifford Wolf 9ec50ca7b9
Merge pull request #896 from YosysHQ/transp_fixes
memory_bram: Fix multiclock make_transp
2019-03-25 14:55:16 +01:00
Clifford Wolf 2bb9632944
Merge pull request #897 from trcwm/libertyfixes
Liberty parser: Accept ranges [A:B], and ignore missing ';'.
2019-03-25 14:47:33 +01:00
Niels Moseley 1f7f54e68e spaces -> tabs 2019-03-25 14:12:04 +01:00
Niels Moseley 9d9cc8a314 EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option) 2019-03-25 12:15:10 +01:00
Niels Moseley 3b3b77291a Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. 2019-03-24 22:54:18 +01:00
David Shah ac6cc88db3 memory_bram: Fix multiclock make_transp
Signed-off-by: David Shah <dave@ds0.me>
2019-03-24 16:21:36 +00:00
Eddie Hung 2507d01b03 Add a pmux-to-shiftx optimisation to proc_mux 2019-03-23 16:45:36 -07:00
Eddie Hung bf83c074c8 Cope with SHREG not having E port; Revert $pmux fine tune 2019-03-23 16:09:38 -07:00
Clifford Wolf ccfa2fe01c Add "mutate -none -mode", "mutate -mode none"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 20:20:32 +01:00
Clifford Wolf 59c44bb61a Add "mutate -s <filename>"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 17:53:09 +01:00
Clifford Wolf 2cf71e2a7b
Merge pull request #893 from YosysHQ/clifford/btormeminit
Memory init support in write_btor
2019-03-23 16:02:01 +01:00
Clifford Wolf 1eff8be8f0 Add support for memory initialization to write_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:40:01 +01:00
Clifford Wolf e78f5a3055 Fix BTOR output tags syntax in writye_btor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:39:42 +01:00
Clifford Wolf 3b796c033c Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
Eddie Hung 098bd5758f Add support for SHREGMAP+$mux, also fine tune $pmux 2019-03-22 23:22:19 -07:00
Eddie Hung 0895093c7c Leftover printf 2019-03-22 19:14:04 -07:00
Eddie Hung 456295eb66 Fixes for multibit 2019-03-22 18:32:42 -07:00