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13,805 Commits 92 Branches 49 Tags 38 MiB
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2352 Commits

Author SHA1 Message Date
Miodrag Milanovic 40f05009e3 Fix CY chaining and CI injection 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 596506b88b Add NX_XCDC_U to wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8909a42796 Better wire check 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 5766555642 Support brams with initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4aaab8f395 start adding wfg model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41a86fdb2c fix 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f4d8ea4c40 Start adding RFB simulation models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8eb099c1f4 remove debug attribute 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 829dd62054 block ram mapping for standard modes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9d6b47466f Add RF initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 7e4aef06e4 Add register file mapping 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 11449ec493 Cleanup not connected ports 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f9f68c3cd1 Split sim models into multiple files and implement few 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 04d3672121 No need for LOC 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 41ae513d60 support other I/O configurations 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 645888cff5 cleanup 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 9a9190b67d enable dff context initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dc16bdd85b DFF reset and context must be in sync 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cb45f8b69d Fixed of mapping and initialization 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 198fc963ca Add new DFF types, and added "-nodffe" option 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0c4bbf7e4b Fix existing DFF mapping and add new types 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 94675a5e0b Fix dff simulation model 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 606439b44c do not leave NX_RAM empty to prevent removing it 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 4cb8e62626 Properly map ff ram 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 1591d258a9 Made NX_CY model more robust 2024-08-15 17:50:36 +02:00
Miodrag Milanovic dac4f04460 add latch mapping, and remove aldff for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cf21b48bfd fix co on nx_cy 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 31f943513b set add_carry property and all inputs to 0 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b6f7383736 break long chains 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ab32dde81b optimized 2024-08-15 17:50:36 +02:00
Miodrag Milanovic da6a62f3a0 Initial carry chain handling pass 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 474ed28aee added no-rw-check, and new rfb models 2024-08-15 17:50:36 +02:00
Miodrag Milanovic a5bfb23b47 start cleaning rams 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 370517b1e6 IO 2024-08-15 17:50:36 +02:00
Miodrag Milanovic fa14c600ff commented remainder of primitives 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8023f921e3 RAM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic b202126c76 IOM 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 71f0984dc9 fixes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ef15325dce removed virtual primitive 2024-08-15 17:50:36 +02:00
Miodrag Milanovic f836de6bcc mark DSPs as TODOs for now 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 8f42d6dace fifo 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 012f0e2952 memory blocks 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 3ed5ea24b2 sortout more blackboxes 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 0ecc2e597f PLLs 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 200e1a7bfe more DSP wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic ce635abc21 NX_DSP/SPLIT 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 60611b936b CDC_U 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 815622f685 CDC_L wrappers 2024-08-15 17:50:36 +02:00
Miodrag Milanovic 827ea11503 start splitting blackboxes and add wrapper techmap 2024-08-15 17:50:36 +02:00
Miodrag Milanovic cfce7dd2f8 remove soc 2024-08-15 17:50:36 +02:00