Commit Graph

10668 Commits

Author SHA1 Message Date
Yosys Bot 48d0aeb094 Bump version 2020-12-30 00:10:06 +00:00
umarcor e61b107072 plugin: enhance no-plugin error 2020-12-29 05:50:04 +01:00
whitequark da1d06d785
Merge pull request #2509 from zachjs/issue-2427
Fix elaboration of whole memory words used as indices
2020-12-29 02:59:09 +00:00
whitequark e609bc4898
Merge pull request #2514 from umarcor/feat/ghdl
makefile: add support for built-in ghdl-yosys-plugin
2020-12-29 02:58:41 +00:00
Yosys Bot 0347b441a1 Bump version 2020-12-29 00:10:04 +00:00
umarcor a652430c71 makefile: add support for built-in ghdl-yosys-plugin
Co-authored-by: Tristan Gingold <tgingold@free.fr>
Co-authored-by: whitequark <whitequark@whitequark.org>
2020-12-28 22:45:00 +01:00
whitequark c718780ff6
Merge pull request #2511 from umarcor/feat/msys2-32
Update MSYS2 build system
2020-12-28 02:33:58 +00:00
whitequark f4a800899c
Merge pull request #2507 from umarcor/fix/msys2
kernel/yosys.h: undef CONST on WIN32
2020-12-28 02:33:30 +00:00
umarcor 0ebce301c1 makefile: rename msys2 to msys2-32, config PREFIX 2020-12-28 02:23:04 +01:00
umarcor 16c4182c74 kernel/yosys.h: undef CONST on WIN32 2020-12-28 02:21:19 +01:00
Yosys Bot f48298347c Bump version 2020-12-28 00:10:04 +00:00
Claire Xen d30063ea65
Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast
CODEOWNERS: add @zachjs as Verilog/AST frontend owner
2020-12-27 16:33:58 +01:00
whitequark cb2283389d
CODEOWNERS: add @zachjs as Verilog/AST frontend owner 2020-12-27 05:00:04 +00:00
Zachary Snow 750831e3e0 Fix elaboration of whole memory words used as indices 2020-12-26 21:47:38 -07:00
Yosys Bot af457ce8d0 Bump version 2020-12-27 00:10:10 +00:00
Miodrag Milanović ce7f06f76e
Merge pull request #2506 from zachjs/const-arg-redeclare
Fix constants bound to redeclared function args
2020-12-26 18:59:06 +01:00
Zachary Snow 1419c8761c Fix constants bound to redeclared function args
The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.
2020-12-26 08:48:01 -07:00
Yosys Bot 4491548037 Bump version 2020-12-24 00:10:08 +00:00
whitequark 54466dc653
Merge pull request #2502 from ldoolitt/master
passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings
2020-12-23 23:36:13 +00:00
whitequark deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
whitequark 8ef6b77dc3
Merge pull request #2476 from zachjs/const-arg-width
Fix constants bound to single bit arguments (fixes #2383)
2020-12-23 23:15:30 +00:00
Larry Doolittle 84c0b5c690 passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings
Verified that the result still builds and passes self-tests
2020-12-23 14:38:25 -08:00
Zachary Snow 999eec5617 genrtlil: fix mux2rtlil generated wire signedness 2020-12-22 17:49:16 -07:00
Yosys Bot 832f6aa777 Bump version 2020-12-23 00:10:07 +00:00
Zachary Snow 8206546c45 Fix constants bound to single bit arguments (fixes #2383) 2020-12-22 17:01:03 -07:00
whitequark d15c63effc
Merge pull request #2499 from whitequark/cxxrtl-fixes
cxxrtl: don't crash generating debug information for unused wires
2020-12-22 12:00:38 +00:00
whitequark f14074d2c2 cxxrtl: don't crash generating debug information for unused wires. 2020-12-22 06:51:38 +00:00
whitequark 2b62b5ef34
Merge pull request #2498 from StefanBruens/Fix_opt_lut
Fix use-after-free in LUT opt pass
2020-12-22 06:15:04 +00:00
whitequark 4949ef1247
Merge pull request #2497 from whitequark/cxxrtl-reflow
cxxrtl: completely rewrite netlist layout code
2020-12-22 06:12:39 +00:00
whitequark 7378194169 cxxrtl: split processes into sync and case nodes.
Similar to the treatment of black boxes, splitting processes into two
scheduling nodes adds sufficient freedom so that netlists with
well-behaved processes (e.g. those emitted by nMigen) can immediately
converge.

Because processes are not emitted into edge-triggered regions, this
approach has comparable performance to -O5 (without -noproc), which
is substantially slower than -O6.
2020-12-22 03:48:09 +00:00
whitequark ac988cfac5 kernel: undef Tcl macros interfering with cxxrtl. 2020-12-22 03:48:09 +00:00
whitequark b2221c1077 cxxrtl: completely rewrite netlist layout code.
The exact shape of C++ code emitted by CXXRTL has a critical effect
on performance, both compile-time and runtime. CXXRTL's performance
greatly improved when it started localizing and inlining wires, not
only because this assists the optimizer and register allocator, but
also because inlining code into edge-triggered regions cuts the time
spent in eval() by at least a factor of two.

However, the logic of netlist layout has always been ad-hoc, fragile,
and very hard to understand and modify. After commit ece25a45, which
introduced outlining, the same logic started being applied to two
distinct netlists at once instead of one, which barely worked.

This commit does four major changes:
  * There is now a single unambiguous source of truth (per subgraph)
    for the layout of any emitted wire.
  * Netlist layout is now done entirely during analysis using well
    known graph algorithms; no graph operations happen when emitting.
  * Netlist layout now happens completely separately for eval() and
    debug_eval() subgraphs.
  * Unreachable (within subgraph scope) netlist nodes are now neither
    emitted nor considered for wire inlining decisions.
The netlist layout code should also now closely match the described
semantics.

As a part of this large cleanup, it includes many miscellaneous
improvements:
  * The "bare minimum" debug level introduced in commit dd6a761d was
    split into two levels; -g1 now emits debug information *only* for
    inputs and state wires, and -g2 now emits debug information for
    all public members. The old behavior matches -g2. This is done
    to avoid bloat on low optimization levels.
  * Debug aliases and inlined connections are now handled separately,
    and complex RHS never interferes with inlined connections.
  * Aliases to outlined wires now carry a pointer to the outline.
  * Cell sync outputs can now be emitted in debug_eval().
  * Black box debug information now includes comb/sync driver flags.
  * The comment emitted for inlined cells is now accurate.
  * Debug information statistics now has less noise.
  * Netlist layout code is now much better documented.

Due to more precise inlining decisions, unmodified (i.e. with no
Yosys script being used) netlists now have much more logic inlined
into edge-triggered regions. On Minerva SoC SRAM, this improves
runtime by 20-25% across compilers and optimization levels.

Due to more precise reachability analysis, much less C++ code is now
emitted, especially at the maximum debug level. On Minerva SoC SRAM,
this improves clang compile time by 30-50% depending on options.
gcc is not affected.
2020-12-22 03:48:09 +00:00
StefanBruens 9396678db4
Fix use-after-free in LUT opt pass
RTLIL::Module::remove(Cell* cell) calls `delete cell`.

Any subsequent accesses of `cell` then causes undefined behavior.
2020-12-22 03:23:42 +01:00
whitequark 3e67ab1ebb
Merge pull request #2479 from zachjs/const-arg-hint
Allow constant function calls in constant function arguments
2020-12-22 01:31:25 +00:00
whitequark df905709ca
Merge pull request #2491 from zachjs/port-bind-sign
Sign extend port connections where necessary
2020-12-22 01:30:29 +00:00
Yosys Bot b62a892b2f Bump version 2020-12-22 00:10:05 +00:00
whitequark e825cf9d73 cxxrtl: simplify logic choosing wire type. NFCI. 2020-12-21 07:24:52 +00:00
whitequark 6f42b26cea cxxrtl: clarify node use-def construction. NFCI. 2020-12-21 07:24:52 +00:00
whitequark 406f866659 cxxrtl: fix typo. 2020-12-21 07:24:52 +00:00
Marcelina Kościelnicka f2932628fc xilinx: Add some missing blackbox cells. 2020-12-21 05:34:26 +01:00
Marcelina Kościelnicka 5ffb676fa9 xilinx: Regenerate cells_xtra.v using Vivado 2020.2 2020-12-21 05:34:26 +01:00
whitequark a679a761b5
Merge pull request #2496 from whitequark/cxxrtl-fixes
cxxrtl: various improvements
2020-12-21 04:32:18 +00:00
whitequark b9721bedf0 cxxrtl: speed up bit repeats (sign extends, etc).
On Minerva SoC SRAM, depending on the compiler, this change improves
overall time by 4-7%.
2020-12-21 02:20:34 +00:00
whitequark 40ca9d038b cxxrtl: speed up commits on clang.
On Minerva SoC SRAM compiled with clang-11, this change cuts commit
time in half (!) and overall time by 20%. When compiled with gcc-10,
there is no difference.
2020-12-21 02:20:30 +00:00
whitequark 3d3ea5099d cxxrtl: use `static inline` instead of `inline` in the C API.
In C, non-static inline functions require an implementation elsewhere
(even though the body is right there in the header). It is basically
never desirable to use those as opposed to static inline ones.
2020-12-20 14:48:16 +00:00
Yosys Bot b90d51e35d Bump version 2020-12-20 00:10:10 +00:00
whitequark ab9e2f4fda
Merge pull request #2487 from whitequark/cxxrtl-outlining
CXXRTL: implement zero-cost full coverage debug information through the magic of outlining🪄🎀🧹
2020-12-19 04:14:31 +00:00
Zachary Snow 0d8e5d965f Sign extend port connections where necessary
- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
2020-12-18 20:33:14 -07:00
Yosys Bot eaf6b551b6 Bump version 2020-12-18 00:10:05 +00:00
Marcelina Kościelnicka 871fc34ad4 xilinx: Add FDDRCPE and FDDRRSE blackbox cells.
These are necessary primitives for proper DDR support on Virtex 2 and
Spartan 3.
2020-12-17 03:25:07 +01:00