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Merge pull request #2509 from zachjs/issue-2427 

Fix elaboration of whole memory words used as indices
This commit is contained in:
whitequark 2020-12-29 02:59:09 +00:00 committed by GitHub
parent e609bc4898 750831e3e0
commit da1d06d785
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 56 additions and 1 deletions
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9
frontends/ast/simplify.cc
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@ -3451,7 +3451,14 @@ replace_fcall_later:;
if (current_scope[str]->children[0]->isConst())
newNode = current_scope[str]->children[0]->clone();
}
else if (at_zero && current_scope.count(str) > 0 && (current_scope[str]->type == AST_WIRE || current_scope[str]->type == AST_AUTOWIRE)) {
else if (at_zero && current_scope.count(str) > 0) {
AstNode *node = current_scope[str];
if (node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY)
newNode = mkconst_int(0, sign_hint, width_hint);
}
break;
case AST_MEMRD:
if (at_zero) {
newNode = mkconst_int(0, sign_hint, width_hint);
}
break;

4
tests/various/memory_word_as_index.data Normal file
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@ -0,0 +1,4 @@
00 04 08 0c
10 14 18 1c
20 24 28 2c
30 34 38 3c

21
tests/various/memory_word_as_index.v Normal file
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@ -0,0 +1,21 @@
`define DATA 64'h492e5c4d7747e032
`define GATE(n, expr) \
module gate``n(sel, out); \
input wire [3:0] sel; \
output wire out; \
reg [63:0] bits; \
reg [5:0] ptrs[15:0]; \
initial bits = `DATA; \
initial $readmemh("memory_word_as_index.data", ptrs); \
assign out = expr; \
endmodule
`GATE(1, bits[ptrs[sel]])
`GATE(2, bits[ptrs[sel][5:0]])
`GATE(3, bits[ptrs[sel]+:1])
module gold(sel, out);
input wire [3:0] sel;
output wire out = `DATA >> (sel * 4);
endmodule

23
tests/various/memory_word_as_index.ys Normal file
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@ -0,0 +1,23 @@
read_verilog memory_word_as_index.v
hierarchy
proc
memory
flatten
opt -full
equiv_make gold gate1 equiv
equiv_simple
equiv_status -assert
delete equiv
equiv_make gold gate2 equiv
equiv_simple
equiv_status -assert
delete equiv
equiv_make gold gate3 equiv
equiv_simple
equiv_status -assert