mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2506 from zachjs/const-arg-redeclare
Fix constants bound to redeclared function args
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commit
ce7f06f76e
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@ -3344,11 +3344,22 @@ skip_dynamic_range_lvalue_expansion:;
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wire->children.insert(wire->children.begin(), arg->clone());
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// args without a range implicitly have width 1
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if (wire->children.back()->type != AST_RANGE) {
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AstNode* range = new AstNode();
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range->type = AST_RANGE;
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wire->children.push_back(range);
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range->children.push_back(mkconst_int(0, true));
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range->children.push_back(mkconst_int(0, true));
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// check if this wire is redeclared with an explicit size
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bool uses_explicit_size = false;
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for (const AstNode *other_child : decl->children)
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if (other_child->type == AST_WIRE && child->str == other_child->str
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&& !other_child->children.empty()
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&& other_child->children.back()->type == AST_RANGE) {
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uses_explicit_size = true;
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break;
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}
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if (!uses_explicit_size) {
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AstNode* range = new AstNode();
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range->type = AST_RANGE;
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wire->children.push_back(range);
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range->children.push_back(mkconst_int(0, true));
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range->children.push_back(mkconst_int(0, true));
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}
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}
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continue;
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}
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@ -50,6 +50,12 @@ module top;
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operation4 = {a, b};
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endfunction
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function automatic integer operation5;
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input x;
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integer x;
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operation5 = x;
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endfunction
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wire [31:0] a;
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assign a = 2;
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@ -70,6 +76,9 @@ module top;
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wire [16:0] x4;
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assign x4 = operation4(a[15:0], 0);
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wire [31:0] x5;
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assign x5 = operation5(64);
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// `define VERIFY
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`ifdef VERIFY
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assert property (a == 2);
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@ -79,5 +88,6 @@ module top;
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assert property (x2 == 4);
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assert property (x3 == 16);
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assert property (x4 == a << 1);
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assert property (x5 == 64);
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`endif
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endmodule
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