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Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast 

CODEOWNERS: add @zachjs as Verilog/AST frontend owner
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Claire Xen 2020-12-27 16:33:58 +01:00 committed by GitHub
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@ -25,6 +25,9 @@ passes/opt/opt_lut.cc @whitequark
# These still override previous lines, so be careful not to
# accidentally disable any of the above rules.
frontends/verilog/ @zachjs
frontends/ast/ @zachjs
techlibs/intel_alm/ @ZirconiumX
# pyosys