Miodrag Milanović
edb95c69a9
Merge pull request #4084 from jix/scopeinfo
...
$scopeinfo support
2024-02-12 09:51:22 +01:00
Martin Povišer
7a3316dd78
synth: Tweak phrasing of `-booth` help
2024-02-08 00:05:15 +01:00
Martin Povišer
a98d363d9d
synth: Run script in full in help mode
2024-02-08 00:05:15 +01:00
Jannis Harder
f728927307
Add builtin celltype $scopeinfo
...
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
Catherine
c7bf0e3b8f
Add new `$check` cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
YRabbit
79c5a06673
gowin: Fix SDP write enable port.
...
This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-30 17:06:59 +10:00
YRabbit
a5fdf3f881
gowin: Change BYTE ENABLE handling.
...
When inferring we allow writing to all bytes for now.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-27 17:19:49 +10:00
YRabbit
ae991abf2e
gowin: fix the BRAM mapping.
...
The primitives used have been corrected and changes have been made to the set of signals.
The empirically established need to set the OCEx signal to 1 when using READ_MODE=0 is reflected.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-01-19 15:26:37 +10:00
Martin Povišer
568418b50b
opt_lut: Replace `-dlogic` with `-tech ice40`
2024-01-15 12:35:21 +01:00
Miodrag Milanovic
627fbc3477
Fix Windows build by forcing initialization order, fixes #4068
2024-01-02 11:26:48 +01:00
Miodrag Milanović
86b8a1c5ae
Merge pull request #4087 from povik/lattice-dp8kc-fix
...
lattice: Fix mapping onto DP8KC for data width 1 or 2
2023-12-21 11:46:11 +01:00
Martin Povišer
c028f25158
lattice: Disable broken port configuration in bram inference
2023-12-21 10:47:40 +01:00
Martin Povišer
fc5c5172f8
lattice: Fix mapping onto DP8KC for data width 1 or 2
2023-12-20 23:42:12 +01:00
Miodrag Milanović
a4ad7cb81a
Merge pull request #4049 from pepijndevos/patch-3
...
Enable bram for Gowin
2023-12-19 08:16:54 +01:00
N. Engelhardt
d87bd7ca3f
Merge pull request #3887 from kivikakk/env-bash
...
tests: use /usr/bin/env for bash.
2023-12-18 16:33:35 +01:00
Miodrag Milanovic
6dc62bd013
Fix out of tree build
2023-12-06 09:56:35 +01:00
Miodrag Milanovic
d71dd5b9bb
Fix out of tree build
2023-12-06 09:11:51 +01:00
Martin Povišer
16ea497d7c
pmgen: Have a single make pattern
...
Remove duplicate %.pmg -> %_pm.h pattern. One of the duplicates overrode
the other, and in some conditions there were build races as to whether
the target directory for the generated header would exist. Instead have
a single rule which is properly generalized.
2023-12-05 18:30:13 +01:00
Martin Povišer
e0fc48e196
quicklogic: Generate `bram_types_sim.v` at build time
2023-12-04 18:21:00 +01:00
Martin Povišer
22cc4aff51
quicklogic: Test TDP36K inference with initial data
2023-12-04 15:52:03 +01:00
N. Engelhardt
f9c8978128
add example memory test
2023-12-04 15:52:03 +01:00
Martin Povišer
e0a6a01ecb
quicklogic: Add `RAM_INIT` to specialized BRAM models
2023-12-04 15:52:03 +01:00
Martin Povišer
4903f99f85
quicklogic: Add missing `RAM_INIT` param on TDP36K sim model
2023-12-04 15:52:03 +01:00
Martin Povišer
b602c0858f
quicklogic: Set initial values on inferred TDP36K
2023-12-04 15:52:03 +01:00
Martin Povišer
b30544d61d
ql_dsp_io_regs: Fix ID strings, constant detection
2023-12-04 15:52:03 +01:00
Martin Povišer
dad85b5178
synth_quicklogic: Fix missing FF mapping
2023-12-04 15:52:03 +01:00
Martin Povišer
532aca28ab
quicklogic: Drop `blackbox` off `adder_carry`
2023-12-04 15:52:03 +01:00
Martin Povišer
e19833f8c7
synth_quiclogic: Fix conditioning of bram passes
2023-12-04 15:52:02 +01:00
Martin Povišer
e43810e13f
ql_dsp_macc: Tune DSP inference code
2023-12-04 15:52:02 +01:00
Martin Povišer
7d738b07da
ql_dsp_*: Clean up
...
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
2023-12-04 15:52:02 +01:00
Martin Povišer
4bb4fd358e
ql_k6n10f: Remove support for parameter-configured DSP variety
2023-12-04 15:52:02 +01:00
N. Engelhardt
b80b1ab8b6
merge brams_final_map.v into brams_map.v
2023-12-04 15:52:02 +01:00
N. Engelhardt
20d864bbde
add dsp inference
2023-12-04 15:52:02 +01:00
N. Engelhardt
6682693888
change ql-bram-types pass to use mode parameter; clean up primitive libraries
2023-12-04 15:52:02 +01:00
N. Engelhardt
48c1fdc33d
add qlf_k6n10f architecture + bram inference
...
(Copied from QuickLogic Yosys plugin repo)
2023-12-04 15:52:02 +01:00
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
gatecat
bf955cc2b0
nexus: Fix format strings to remove space padding
...
Signed-off-by: gatecat <gatecat@ds0.me>
2023-12-03 10:36:34 +01:00
Pepijn de Vos
f19c6b4415
Enable bram for Gowin
2023-12-03 10:17:28 +01:00
N. Engelhardt
beaae79e73
Merge pull request #4021 from povik/booth-wallace
...
Change `booth` architecture for improved delay, similar signed/unsigned results
2023-11-27 16:26:03 +01:00
Martin Povišer
de16cd253d
synth_lattice: Enable `booth` by default on XO3
2023-11-22 15:47:11 +01:00
Lofty
5c96746309
ice40: fix -noabc9
2023-11-17 12:49:17 +00:00
Lofty
309558767d
gowin: fix typo
2023-11-14 22:37:29 +00:00
N. Engelhardt
8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again
...
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 17:29:57 +01:00
N. Engelhardt
52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work
...
MachXO3 QoR improvements
2023-11-13 16:56:06 +01:00
N. Engelhardt
3fef81b537
Merge pull request #4028 from povik/cmp2softlogic
...
synth_lattice: Optionally do constant comparisons in soft logic
2023-11-13 16:53:04 +01:00
Lofty
7ae4041e20
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
Martin Povišer
3ffa4b5e5d
synth_lattice: Wire up `cmp2softlogic` as an option
2023-11-13 10:42:12 +01:00
Martin Povišer
f7d4a855c6
techlibs: Add `cmp2softlogic.v` to common
2023-11-13 10:42:12 +01:00
Krystine Sherwin
83d2f4f334
techlibs: fix typo in help message
2023-11-13 16:29:52 +13:00
Martin Povišer
fed2720999
synth_lattice: Optimize flip-flop memories better
...
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
2023-11-07 16:29:56 +01:00