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Merge pull request #4087 from povik/lattice-dp8kc-fix 

lattice: Fix mapping onto DP8KC for data width 1 or 2
This commit is contained in:
Miodrag Milanović 2023-12-21 11:46:11 +01:00 committed by GitHub
parent a4ad7cb81a c028f25158
commit 86b8a1c5ae
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2 changed files with 18 additions and 2 deletions
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4
techlibs/lattice/brams_8kc.txt
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@ -32,6 +32,10 @@ ram block $__PDPW8KC_ {
cost 64;
init no_undef;
port sr "R" {
# width 2 cannot be supported because of quirks
# of the primitive, and memlib requires us to
# remove width 1 as well
width 4 9 18;
clock posedge;
clken;
option "RESETMODE" "SYNC" {

16
techlibs/lattice/brams_map_8kc.v
View File

@ -38,8 +38,20 @@ endfunction
wire [8:0] DOA;
wire [8:0] DOB;
wire [8:0] DIA = PORT_A_WR_DATA;
wire [8:0] DIB = PORT_B_WR_DATA;
wire [8:0] DIA;
wire [8:0] DIB;
case(PORT_A_WIDTH)
1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};
2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};
default: assign DIA = PORT_A_WR_DATA;
endcase
case(PORT_B_WIDTH)
1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};
2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};
default: assign DIB = PORT_B_WR_DATA;
endcase
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;