From fc5c5172f81189b67a93f85a189bf77f04fda971 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 20 Dec 2023 23:23:02 +0100 Subject: [PATCH 1/2] lattice: Fix mapping onto DP8KC for data width 1 or 2 --- techlibs/lattice/brams_map_8kc.v | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/techlibs/lattice/brams_map_8kc.v b/techlibs/lattice/brams_map_8kc.v index 6783e5b29..b57250fc7 100644 --- a/techlibs/lattice/brams_map_8kc.v +++ b/techlibs/lattice/brams_map_8kc.v @@ -38,8 +38,20 @@ endfunction wire [8:0] DOA; wire [8:0] DOB; -wire [8:0] DIA = PORT_A_WR_DATA; -wire [8:0] DIB = PORT_B_WR_DATA; +wire [8:0] DIA; +wire [8:0] DIB; + +case(PORT_A_WIDTH) + 1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx}; + 2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx}; + default: assign DIA = PORT_A_WR_DATA; +endcase + +case(PORT_B_WIDTH) + 1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx}; + 2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx}; + default: assign DIB = PORT_B_WR_DATA; +endcase assign PORT_A_RD_DATA = DOA; assign PORT_B_RD_DATA = DOB; From c028f251585b1e42a7c493afb4b428408daa47c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 21 Dec 2023 10:22:52 +0100 Subject: [PATCH 2/2] lattice: Disable broken port configuration in bram inference --- techlibs/lattice/brams_8kc.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/techlibs/lattice/brams_8kc.txt b/techlibs/lattice/brams_8kc.txt index 3afbeda07..f254c46aa 100644 --- a/techlibs/lattice/brams_8kc.txt +++ b/techlibs/lattice/brams_8kc.txt @@ -32,6 +32,10 @@ ram block $__PDPW8KC_ { cost 64; init no_undef; port sr "R" { + # width 2 cannot be supported because of quirks + # of the primitive, and memlib requires us to + # remove width 1 as well + width 4 9 18; clock posedge; clken; option "RESETMODE" "SYNC" {