Miodrag Milanovic
ae7daf99f4
Verific: Add attributes to module instantiation
2024-02-12 09:53:47 +01:00
Ethan Mahintorabi
ff578ecabd
fix formatting
...
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-05 07:23:04 +00:00
Ethan Mahintorabi
bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer
...
The following SV module at HEAD imported with verific,
```systemverilog
module my_module(
input logic [4:0] a,
input logic clk,
input logic enable,
output logic [4:0] z
);
reg [4:0] pipeline_register;
always @(posedge clk) begin
pipeline_register <= enable ? a : pipeline_register;
end
assign z = pipeline_register;
endmodule : my_module
```
results in the following output verilog
```systemverilog
/* Generated by 0.36 */
(* top = 1 *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
wire [4:0] _0_;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
input [4:0] a;
wire [4:0] a;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
input clk;
wire clk;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
input enable;
wire enable;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
output [4:0] z;
wire [4:0] z;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
\$aldff #(
.ALOAD_POLARITY(32'd1),
.CLK_POLARITY(32'd1),
.WIDTH(32'd5)
) _1_ (
.AD(5'hxx),
.ALOAD(1'h0),
.CLK(clk),
.D(_0_),
.Q(z)
);
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
\$mux #(
.WIDTH(32'd5)
) _2_ (
.A(z),
.B(a),
.S(enable),
.Y(_0_)
);
endmodule
```
Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.
My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-05 07:10:25 +00:00
Miodrag Milanovic
db1de5fe5d
verific: add option to skip simplifying complex ports
2024-01-30 16:33:44 +01:00
Miodrag Milanovic
1764c0ee3c
Fix verific clocking when no driver exist
2024-01-18 08:47:04 +01:00
Miodrag Milanovic
96fecf0716
Revert "Add attributes to module instantiation"
...
This reverts commit 8f207eed1b
.
2023-12-04 16:37:01 +01:00
Miodrag Milanovic
8f207eed1b
Add attributes to module instantiation
2023-11-23 11:01:49 +01:00
N. Engelhardt
5fb1264db5
verific: don't try to import attributes from nullptr
2023-11-14 15:05:24 +01:00
N. Engelhardt
93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr
...
memory_libmap: look for ram_style attributes on surrounding signals
2023-11-06 16:25:38 +01:00
Miodrag Milanovic
f06d56d224
Handling non-existing location in verific logs
2023-11-03 08:06:16 +01:00
Miodrag Milanovic
4eb18e1f07
change verific log callback api
2023-11-01 08:13:27 +01:00
N. Engelhardt
833b67af80
verific: import attributes on ports
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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
2023-10-20 18:31:41 +02:00
Miodrag Milanovic
d473a207a1
Preserve VHDL architecture name in attribute
2023-10-12 09:17:06 +02:00
Jannis Harder
4ed708836a
verific: Use CellBaseName to identify top modules
2023-10-10 11:51:16 +02:00
Miodrag Milanović
a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname
...
verific: save original module name
2023-10-05 19:41:00 +02:00
Jannis Harder
47a4b790f8
verific: Pass top modules to static elaboration when using hierarchy
2023-10-05 16:51:49 +02:00
Jannis Harder
23b9e61c47
verific: Pass list of top modules to static elaboration
2023-10-05 16:51:49 +02:00
Miodrag Milanovic
268fe92d22
verific: save original module name
2023-10-05 11:22:40 +02:00
Jannis Harder
563a56d9ff
verific: Improve interaction between -L, -work and bind statements
2023-10-03 15:52:01 +02:00
Miodrag Milanovic
f193ebdded
Verific: add default parameters to modules
2023-09-27 16:57:18 +02:00
Miodrag Milanovic
18855f23ce
Set src attribute for verific with full info
2023-09-19 12:00:10 +02:00
Jannis Harder
0e8a4adb59
verific: Update YOSYSHQ_VERIFIC_API_VERSION
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
27ac912709
Support import of $future_ff
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
9c255c98b1
unescape string tag attribute
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
54050a8c16
Basic support for tag primitives
2023-09-13 11:32:36 +02:00
Miodrag Milanovic
7b134c2a8c
verific - respect order of read and write for rams
2023-09-12 11:56:15 +02:00
Miodrag Milanovic
19d5293657
when blackboxing no need to know missing modules
2023-07-31 09:18:54 +02:00
Miodrag Milanovic
372760af57
spaces to tabs
2023-07-25 09:40:30 +02:00
Miodrag Milanovic
3989181cd6
Add ability to blackbox modules/units from file while reading with verific
2023-07-25 09:40:30 +02:00
N. Engelhardt
21686f0d9d
verific: import src attribute on $memrd/$memwr cells
2023-06-23 19:41:36 +02:00
Miodrag Milanovic
aff0065646
Use defaultvalue for init values of input ports
2023-06-21 13:21:34 +02:00
Miodrag Milanovic
75cf79588e
Add ability for user plugin to add new verific log callback
2023-06-12 10:01:01 +02:00
Miodrag Milanovic
ecd289c100
Fix importing parametrized VHDL entity
2023-05-23 08:25:08 +02:00
Jannis Harder
ec47bf1745
verific: Handle conditions when using sva_at_only in VerificClocking
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This handles conditions on clocked concurrent assertions in unclocked
procedural contexts.
2023-04-21 16:51:42 +02:00
Jannis Harder
390d1c583a
verific: Fix enum_values support and signed attribute values
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This uses the same constant parsing for enum_values and for attributes
and extends it to handle signed values as those are used for enums that
implicitly use the int type.
2023-03-15 09:51:36 +01:00
Miodrag Milanovic
a30894e5fa
Handle more wide case selector types
2023-02-27 09:24:04 +01:00
Miodrag Milanovic
109b88c379
For case select values use Sa instead of Sx and Sz
2023-02-08 09:22:48 +01:00
Miodrag Milanovic
e7e37df91b
Add verific import support for OPER_WIDE_CASE_SELECT_BOX
2023-02-06 09:28:23 +01:00
Miodrag Milanovic
6574553189
Fixes for some of clang scan-build detected issues
2023-01-17 12:58:08 +01:00
Miodrag Milanovic
b867dee241
respect noblackbox attribute in verific
2022-12-15 08:17:53 +01:00
Miodrag Milanović
9362fdb4c6
Merge pull request #3568 from YosysHQ/verific_msg
...
Set all Verific messages of certain type to other
2022-12-05 16:22:44 +01:00
Miodrag Milanovic
34a64aa322
set VERI-1063 explicitly
2022-12-02 17:11:17 +01:00
Miodrag Milanovic
2dd55d73a0
reset elaboration error after rewriter
2022-11-30 17:26:48 +01:00
Miodrag Milanovic
bfd79845b6
Set all verific messages of certain type to other
2022-11-30 16:42:37 +01:00
Miodrag Milanovic
f764cd1655
update documentation
2022-11-25 14:27:30 +01:00
Miodrag Milanovic
b0be19c126
Support importing verilog configurations using Verific
2022-11-25 13:02:11 +01:00
Miodrag Milanovic
59b6ac47c9
Add additional help info
2022-10-31 18:04:34 +01:00
Miodrag Milanovic
6fb80bce15
Enable importing blackbox modules only
2022-10-31 10:51:28 +01:00
Miodrag Milanovic
e702f2894a
Support for reading liberty files using verific
2022-10-31 10:15:05 +01:00
Miodrag Milanovic
48628fbf5a
Skip verific primitives and operators import by default
2022-10-14 17:41:24 +02:00