mirror of https://github.com/YosysHQ/yosys.git
verific: Use CellBaseName to identify top modules
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3e22791810
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4ed708836a
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@ -2573,7 +2573,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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continue;
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nl->AddAtt(new Att(" \\top", NULL));
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nl_todo.emplace(nl->CellBaseName(), nl);
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cell_name = nl->Owner()->Name();
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cell_name = nl->CellBaseName();
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}
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if (top.empty()) cell_name = top;
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@ -2595,7 +2595,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
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if (nl_done.count(it->first) == 0) {
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VerificImporter importer(false, false, false, false, false, false, false);
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nl_done[it->first] = it->second;
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importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name);
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importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == cell_name);
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}
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nl_todo.erase(it);
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}
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@ -3801,7 +3801,7 @@ struct VerificPass : public Pass {
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VerificImporter importer(mode_gates, mode_keep, mode_nosva,
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mode_names, mode_verific, mode_autocover, mode_fullinit);
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nl_done[it->first] = it->second;
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importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name()));
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importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->CellBaseName()));
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}
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nl_todo.erase(it);
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}
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