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8075 Commits

Author SHA1 Message Date
Eddie Hung 3753760971 Bump ABCREV 2020-01-06 16:20:58 -08:00
Eddie Hung 66698cb6fd
Merge pull request #1617 from YosysHQ/eddie/abc9_dsp_refactor 
Refactor abc9's DSP48E1 handling
 2020-01-06 15:00:16 -08:00
Eddie Hung 28bf712372 Wrap arrival functions inside `YOSYS too 2020-01-06 11:55:56 -08:00
Eddie Hung 898a8fa7ac
Merge pull request #1616 from nakengelhardt/abc_scratchpad_arg_warn 
error if multiple -g options are given for abc
 2020-01-06 11:39:59 -08:00
Eddie Hung 27c150bfcc Fix return value of arrival time functions, fix word 2020-01-06 11:39:08 -08:00
Eddie Hung 7738d608e3 Bump ABCREV for upstream fix 2020-01-06 11:14:05 -08:00
N. Engelhardt fcc1c14adc error if multiple -g options are given for abc 2020-01-06 19:10:13 +01:00
Eddie Hung 89b88ea17f
Merge pull request #1582 from nakengelhardt/abc_scratchpad_script 
Check scratchpad for abc options
 2020-01-06 09:42:26 -08:00
N. Engelhardt 7764b62d23 check scratchpad for arguments in abc pass too 2020-01-06 10:46:44 +01:00
N. Engelhardt b376548fb9 inherit default values when checking scratchpad for arguments 2020-01-06 10:46:10 +01:00
Miodrag Milanović 2e0da68528
Merge pull request #1611 from YosysHQ/mmicko/wrapcarry_fix 
Valid to have attribute starting with SB_CARRY.
 2020-01-05 20:21:04 +01:00
Miodrag Milanovic c5d28f5d6b Valid to have attribute starting with SB_CARRY. 2020-01-04 19:00:44 +01:00
N. Engelhardt b2ad781b07 share codepath for scratchpad argument handling with command arguments 2020-01-03 14:11:41 +01:00
N. Engelhardt 341fd872b5 Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script 2020-01-03 12:28:48 +01:00
Eddie Hung 50b68777d3 Drive $[ABCD] explicitly 2020-01-02 13:28:37 -08:00
whitequark f8d5920a7e
Merge pull request #1604 from whitequark/unify-ram-naming 
Harmonize BRAM/LUTRAM descriptions across all of Yosys
 2020-01-02 21:06:17 +00:00
Eddie Hung 3012e9eebc Merge remote-tracking branch 'origin/master' into eddie/abc9_dsp_refactor 2020-01-02 12:48:07 -08:00
Clifford Wolf ef6548203c
Merge pull request #1609 from YosysHQ/clifford/fix1596 
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
 2020-01-02 19:57:27 +01:00
Clifford Wolf 3edb2e708b Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2020-01-02 18:58:45 +01:00
Eddie Hung d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime 
"abc -dff" to no longer retime by default
 2020-01-02 08:46:24 -08:00
Eddie Hung a8f6688888
Merge pull request #1608 from YosysHQ/eddie/ifndef_YOSYS 
ifdef __ICARUS__ -> ifndef YOSYS
 2020-01-02 08:46:02 -08:00
Eddie Hung d0d3ab8f67 ifndef __ICARUS__ -> ifdef YOSYS 2020-01-01 17:33:47 -08:00
Eddie Hung 3d98a96273 ifdef __ICARUS__ -> ifndef YOSYS 2020-01-01 17:33:10 -08:00
Eddie Hung db04161eca Rework abc9's DSP48E1 model 2020-01-01 17:30:26 -08:00
Eddie Hung 9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung 52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanović 6620b4e94e
Merge pull request #1605 from YosysHQ/iopad_fix 
iopad mapping should take care of existing io buffers
 2020-01-01 17:46:45 +01:00
Eddie Hung 3deec51ddc Fix anlogic async flop mapping 2020-01-01 08:43:16 -08:00
Miodrag Milanovic a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Miodrag Milanovic e0c879684f take skip wire bits into account 2020-01-01 16:13:14 +01:00
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys. 
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
 2020-01-01 12:30:00 +00:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung 22fe931c86 Grammar 2019-12-30 15:07:15 -08:00
Eddie Hung 543bd2de6c Update timings for Xilinx S7 cells 2019-12-30 14:36:07 -08:00
Eddie Hung 79448f9be0 Update doc that "-retime" calls abc with "-dff -D 1" 2019-12-30 13:28:29 -08:00
Eddie Hung c9e3b26412 Disable synth_gowin -abc9 as it offers no advantages yet 2019-12-30 13:28:29 -08:00
Eddie Hung aa6d06c1b5 Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well"" 
This reverts commit 6008bb7002.
 2019-12-30 13:28:29 -08:00
Eddie Hung 566d9fb77f Revert "ABC to call retime all the time" 
This reverts commit 9aa94370a5.
 2019-12-30 13:28:29 -08:00
Miodrag Milanović c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Eddie Hung c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588 
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
 2019-12-30 10:01:02 -08:00
Eddie Hung ce6e4f6341
Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5 
Nitpick cleanup for ecp5
 2019-12-30 10:00:47 -08:00
Miodrag Milanovic f9749c202c Fix new tests 2019-12-28 16:43:19 +01:00
Miodrag Milanovic 8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Miodrag Milanovic a82c701668 Make test without iopads 2019-12-28 16:22:24 +01:00
Miodrag Milanovic 509da7ed1a Revert "Fix xilinx tests, when iopads are default" 
This reverts commit 477e43d921.
 2019-12-28 16:12:45 +01:00
Eddie Hung 011f749ecf Update resource count 2019-12-28 02:15:11 -08:00
Eddie Hung 71906fab51 Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
Eddie Hung d45869855c Add #1598 testcase 2019-12-27 16:44:57 -08:00