Clifford Wolf
2a681909df
Merge pull request #724 from whitequark/equiv_opt
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equiv_opt: new command, for verifying optimization passes
2018-12-16 15:54:26 +01:00
Clifford Wolf
a2154c1be0
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
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memory_bram: Fix initdata bit order after shuffling
2018-12-16 15:53:44 +01:00
Clifford Wolf
ceffa66dbd
Merge pull request #730 from smunaut/ffssr_dont_touch
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ice40: Honor the "dont_touch" attribute in FFSSR pass
2018-12-16 15:50:42 +01:00
Clifford Wolf
f481ad4d44
Merge pull request #729 from whitequark/write_verilog_initial
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write_verilog: correctly map RTLIL `sync init`
2018-12-16 15:50:16 +01:00
Clifford Wolf
0c69f1d777
Merge pull request #725 from olofk/ram4k-init
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Only use non-blocking assignments of SB_RAM40_4K for yosys
2018-12-16 15:42:04 +01:00
Clifford Wolf
a1fb5b1e4b
Merge pull request #714 from daveshah1/abc_preserve_naming
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Proof-of-concept: preserve naming through ABC using dress
2018-12-16 15:41:30 +01:00
Clifford Wolf
9522eee02f
Merge pull request #723 from whitequark/synth_ice40_map_gates
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synth_ice40: split `map_gates` off `fine`
2018-12-16 15:30:08 +01:00
Clifford Wolf
19ca4e2ac3
Merge pull request #722 from whitequark/rename_src
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rename: add -src, for inferring names from source locations
2018-12-16 15:28:29 +01:00
Clifford Wolf
556341a77f
Merge pull request #720 from whitequark/master
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lut2mux: handle 1-bit INIT constant in $lut cells
2018-12-16 15:27:23 +01:00
Sylvain Munaut
58fb2ac818
verilog_parser: Properly handle recursion when processing attributes
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Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-14 12:48:00 +01:00
David Shah
4c59447168
deminout: Consider $tribuf cells
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 17:17:40 +00:00
David Shah
d3fe9465f3
deminout: Don't demote constant-driven inouts to inputs
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-12 16:50:46 +00:00
Graham Edgecombe
4fef9689ab
memory_bram: Fix initdata bit order after shuffling
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In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
2018-12-11 21:02:49 +00:00
Clifford Wolf
0b9bb852c6
Add yosys-smtbmc support for btor witness
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-10 03:43:07 +01:00
Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
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This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
Clifford Wolf
47a5dfdaa4
Add "yosys-smtbmc --btorwit" skeleton
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:59:27 +01:00
Clifford Wolf
ed3c57fad3
Fix btor init value handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-08 06:21:31 +01:00
whitequark
7fe770a441
write_verilog: correctly map RTLIL `sync init`.
2018-12-07 18:55:08 +00:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
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This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
David Shah
435776120a
Merge pull request #727 from whitequark/opt_lut
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opt_lut: leave intact LUTs with cascade feeding module outputs
2018-12-07 17:17:26 +00:00
whitequark
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
whitequark
9eb03d458d
opt_lut: show original truth table for both cells.
2018-12-07 17:04:41 +00:00
whitequark
a8ab722824
opt_lut: add -limit option, for debugging misoptimizations.
2018-12-07 16:36:26 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
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In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
David Shah
1dfb2fecab
abc: Preserve naming through ABC using 'dress' command
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Signed-off-by: David Shah <dave@ds0.me>
2018-12-06 15:05:07 +00:00
whitequark
6e559ee3c7
synth_ice40: split `map_gates` off `fine`.
2018-12-06 12:04:39 +00:00
Clifford Wolf
7d1088afc4
Add missing .gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:37 +01:00
Clifford Wolf
643f858acf
Bugfix in opt_expr handling of a<0 and a>=0
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:21 +01:00
Clifford Wolf
910d94b212
Verific updates
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:21:50 +01:00
whitequark
a9baee4b24
rename: add -src, for inferring names from source locations.
2018-12-05 20:35:13 +00:00
whitequark
d1f2cb01dc
lut2mux: handle 1-bit INIT constant in $lut cells.
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This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
2018-12-05 19:27:48 +00:00
whitequark
88217d0157
opt_lut: simplify type conversion. NFC.
2018-12-05 19:12:02 +00:00
Clifford Wolf
1bb728e24f
Merge pull request #709 from smunaut/issue_708
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Make return value of $clog2 signed
2018-12-05 09:19:44 -08:00
Clifford Wolf
728a251a95
Merge pull request #718 from whitequark/gate2lut
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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
2018-12-05 09:16:35 -08:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
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This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Clifford Wolf
e115303129
Merge pull request #713 from Diego-HR/master
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Changes in GoWin synth commands and ALU primitive support
2018-12-05 09:08:30 -08:00
Clifford Wolf
1a260ce89b
Merge pull request #712 from mmicko/anlogic-support
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Initial support for Anlogic FPGA
2018-12-05 09:08:04 -08:00
Clifford Wolf
2d98db73e3
Rename opt_lut.cpp to opt_lut.cc
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-05 18:03:58 +01:00
Clifford Wolf
50a94ce4fc
Merge pull request #717 from whitequark/opt_lut
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Add a new opt_lut pass, which combines inefficiently packed LUTs
2018-12-05 09:02:13 -08:00
Clifford Wolf
11323665af
Merge pull request #716 from whitequark/ice40_unlut
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Extract ice40_unlut pass from ice40_opt
2018-12-05 08:59:21 -08:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
e603484070
opt_lut: always prefer to eliminate 1-LUTs.
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These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
2018-12-05 16:30:37 +00:00
whitequark
59eea0183f
opt_lut: collect and display statistics.
2018-12-05 16:30:37 +00:00
whitequark
e54c7e951c
opt_lut: refactor to use a worker. NFC.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
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Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00