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12 Commits

Author SHA1 Message Date
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf 313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf 264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf 4cc4400514 improved iCE40 SB_RAM40_4K simulation model 2015-04-25 20:01:37 +02:00
Clifford Wolf 82a4722f46 More iCE40 bram improvements 2015-04-25 18:04:57 +02:00
Clifford Wolf 308a59aa18 iCE40 bram tests and fixes 2015-04-24 08:32:07 +02:00
Clifford Wolf 1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models 2015-04-19 21:37:40 +02:00
Clifford Wolf 31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name 2015-04-16 12:09:14 +02:00
Clifford Wolf 0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf 06ce496f8d more cells in ice40 cell library 2015-04-14 13:44:43 +02:00
Clifford Wolf 42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00