riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,512 Commits 75 Branches 48 Tags 61 MiB
Commit Graph

637 Commits

Author SHA1 Message Date
Eddie Hung 58e512ab70 Add comment 2019-08-07 09:54:27 -07:00
Eddie Hung f20acbc813 Revert "Add TODO" 
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
 2019-08-07 09:54:27 -07:00
Eddie Hung 789585a744 Add TODO 2019-08-07 09:54:27 -07:00
Eddie Hung 8a8c1d7857 Compute box_lookup just once 2019-08-07 09:54:27 -07:00
Clifford Wolf 100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Miodrag Milanovic 35d28de478 Visual Studio build fix 2019-07-31 09:10:24 +02:00
Eddie Hung 5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters 
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
 2019-07-16 08:53:47 -07:00
Eddie Hung ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix 
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
 2019-07-16 08:52:14 -07:00
Miodrag Milanovic 2b469e82a7 Fix check logic in extract_fa 2019-07-16 10:35:18 +02:00
Eddie Hung 9b91d815b5 If ConstEval fails do not log_abort() but return gracefully 2019-07-13 04:13:57 -07:00
Eddie Hung fb062c3426 Add comment 2019-07-13 00:52:21 -07:00
Eddie Hung e9bdc86c0e duplicate -> clone 2019-07-12 19:33:02 -07:00
Eddie Hung be0cb7f4b8 More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7d583f9e57 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 83f23a24a8 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 1adbfb5533 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 39a7c7c54c More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 91c07be196 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 399e1ec870 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 58dbb28fd3 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7dc15bdd2d Do not double count cells in abc 2019-07-12 08:22:26 -07:00
Eddie Hung c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
whitequark ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung 3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung 4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung 137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung 6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung c226af3f56 Fix spacing 2019-06-26 20:03:34 -07:00
Eddie Hung 26efd6f0a9 Support more than one port in the abc_scc_break attr 2019-06-26 19:57:54 -07:00
Eddie Hung d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Clifford Wolf ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 19:24:41 +02:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf 9286b6f013 Add "muxcover -freedecode" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 10:02:10 +02:00
Eddie Hung 54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00