Claire Wolf
30642e9570
Merge pull request #1629 from YosysHQ/mwk/edif-z
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edif: Just ignore connections to 'z
2020-01-21 18:35:15 +01:00
Marcin Kościelnicki
55f86eda36
edif: Just ignore connections to 'z
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Connecting a const 'z to a net should be equivalent to not connecting it
at all, so let's just ignore such connections on output.
2020-01-13 14:49:31 +01:00
Miodrag Milanovic
6888799c75
remove whitespace
2020-01-10 12:38:03 +01:00
Miodrag Milanovic
2bcd55f1ae
Export wire properties as well in EDIF
2020-01-10 12:33:58 +01:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
Clifford Wolf
03237de686
Fix "write_edif -gndvccy"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 12:59:07 -08:00
Clifford Wolf
54dc33b905
Add "write_edif -gndvccy"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-01-17 13:33:11 +01:00
Clifford Wolf
115ca57647
Add "write_edif -attrprop"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-05 09:41:30 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
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o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
4a8c131fa7
Fix the fixed handling of x-bits in EDIF back-end
2017-07-11 17:45:29 +02:00
Clifford Wolf
479be3cec7
Fix handling of x-bits in EDIF back-end
2017-07-11 17:38:19 +02:00
Clifford Wolf
850f8299a9
Fix EDIF: portRef member 0 is always the MSB bit
2017-03-19 14:53:28 +01:00
Clifford Wolf
c7d1286728
Improve "write_edif" help message
2017-02-25 16:35:53 +01:00
Clifford Wolf
dfddf391f9
Move EdifNames out of double-private namespace
2017-02-25 16:29:27 +01:00
Clifford Wolf
8c61ecdd6e
Clean up edif code, swap bit indexing of "upto" ports
2017-02-25 16:28:34 +01:00
Johann Klammer
6d7a77dbf6
Did as you requested, /but/...
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Now the nets are wired in reverse again because the netlister still uses zero-based indices.
2017-02-24 13:18:49 +01:00
Johann Klammer
06df86aae3
add options for edif flavors
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*to force renames on wide ports
*to choose array delimiters
*to choose up or downwards indices
2017-02-23 19:42:37 +01:00
Clifford Wolf
4e80ce97a8
Add warning about x/z bits left unconnected in EDIF output
2017-02-14 12:49:35 +01:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
3920bf58d0
Fixed some typos
2016-04-05 08:18:21 +02:00
Clifford Wolf
d117893007
Added "write_edif -nogndvcc"
2016-03-08 21:30:45 +01:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
6978f3a77b
Added EDIF backend support for multi-bit cell ports
2015-02-01 15:43:35 +01:00
Clifford Wolf
4569a747f8
Renamed SIZE() to GetSize() because of name collision on Win32
2014-10-10 17:07:24 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
5dce303a2a
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
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git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
6aa792c864
Replaced more old SigChunk programming patterns
2014-07-24 23:10:58 +02:00
Clifford Wolf
c094c53de8
Removed RTLIL::SigSpec::optimize()
2014-07-23 20:32:28 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
038eac7414
Better handling of nameDef and nameRef in edif backend
2014-02-21 13:40:43 +01:00
Clifford Wolf
f3ff29d410
Fixed instantiating multi-bit ports in edif backend
2014-02-21 13:10:36 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
28093d9dd2
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
ba305a7ca6
Improved comments on topological sort in edif backend
2013-11-04 08:34:15 +01:00
Clifford Wolf
cd0fe7d786
Added simple topological sort to edif backend
2013-11-03 22:01:32 +01:00
Clifford Wolf
1dcb683fcb
Write yosys version to output files
2013-11-03 21:41:39 +01:00
Clifford Wolf
d9fa1e5a1d
Fixed hex string generation bug in edif backend
2013-10-27 08:21:05 +01:00