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module GP_DFFS ( input D , CLK , nSET , output reg Q ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DFFSR # (
. INIT ( INIT ) ,
. SRMODE ( 1'b1 ) ,
) _ TECHMAP_REPLACE_ (
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. D ( D ) ,
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. CLK ( CLK ) ,
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. nSR ( nSET ) ,
. Q ( Q )
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) ;
endmodule
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module GP_DFFR ( input D , CLK , nRST , output reg Q ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DFFSR # (
. INIT ( INIT ) ,
. SRMODE ( 1'b0 ) ,
) _ TECHMAP_REPLACE_ (
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. D ( D ) ,
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. CLK ( CLK ) ,
. nSR ( nRST ) ,
. Q ( Q )
) ;
endmodule
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module GP_DFFSI ( input D , CLK , nSET , output reg nQ ) ;
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parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DFFSRI # (
. INIT ( INIT ) ,
. SRMODE ( 1'b1 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
. CLK ( CLK ) ,
. nSR ( nSET ) ,
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. nQ ( nQ )
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) ;
endmodule
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module GP_DFFRI ( input D , CLK , nRST , output reg nQ ) ;
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parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DFFSRI # (
. INIT ( INIT ) ,
. SRMODE ( 1'b0 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
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. CLK ( CLK ) ,
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. nSR ( nRST ) ,
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. nQ ( nQ )
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) ;
endmodule
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module GP_DLATCHS ( input D , nCLK , nSET , output reg Q ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DLATCHSR # (
. INIT ( INIT ) ,
. SRMODE ( 1'b1 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
. nCLK ( nCLK ) ,
. nSR ( nSET ) ,
. Q ( Q )
) ;
endmodule
module GP_DLATCHR ( input D , nCLK , nRST , output reg Q ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DLATCHSR # (
. INIT ( INIT ) ,
. SRMODE ( 1'b0 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
. nCLK ( nCLK ) ,
. nSR ( nRST ) ,
. Q ( Q )
) ;
endmodule
module GP_DLATCHSI ( input D , nCLK , nSET , output reg nQ ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DLATCHSRI # (
. INIT ( INIT ) ,
. SRMODE ( 1'b1 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
. nCLK ( nCLK ) ,
. nSR ( nSET ) ,
. nQ ( nQ )
) ;
endmodule
module GP_DLATCHRI ( input D , nCLK , nRST , output reg nQ ) ;
parameter [ 0 : 0 ] INIT = 1'bx ;
GP_DLATCHSRI # (
. INIT ( INIT ) ,
. SRMODE ( 1'b0 ) ,
) _ TECHMAP_REPLACE_ (
. D ( D ) ,
. nCLK ( nCLK ) ,
. nSR ( nRST ) ,
. nQ ( nQ )
) ;
endmodule
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module GP_OBUFT ( input IN , input OE , output OUT ) ;
GP_IOBUF _ TECHMAP_REPLACE_ (
. IN ( IN ) ,
. OE ( OE ) ,
. IO ( OUT ) ,
. OUT ()
) ;
endmodule
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module \ $ lut ( A , Y ) ;
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parameter WIDTH = 0 ;
parameter LUT = 0 ;
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(* force_downto *)
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input [ WIDTH - 1 : 0 ] A ;
output Y ;
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generate
if ( WIDTH = = 1 ) begin
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if ( LUT = = 2'b01 ) begin
GP_INV _ TECHMAP_REPLACE_ ( . OUT ( Y ) , . IN ( A [ 0 ] ) ) ;
end
else begin
GP_2LUT # ( . INIT ( { 2'b00 , LUT } ) ) _ TECHMAP_REPLACE_ ( . OUT ( Y ) ,
. IN0 ( A [ 0 ] ) , . IN1 ( 1'b0 ) ) ;
end
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end else
if ( WIDTH = = 2 ) begin
GP_2LUT # ( . INIT ( LUT ) ) _ TECHMAP_REPLACE_ ( . OUT ( Y ) ,
. IN0 ( A [ 0 ] ) , . IN1 ( A [ 1 ] ) ) ;
end else
if ( WIDTH = = 3 ) begin
GP_3LUT # ( . INIT ( LUT ) ) _ TECHMAP_REPLACE_ ( . OUT ( Y ) ,
. IN0 ( A [ 0 ] ) , . IN1 ( A [ 1 ] ) , . IN2 ( A [ 2 ] ) ) ;
end else
if ( WIDTH = = 4 ) begin
GP_4LUT # ( . INIT ( LUT ) ) _ TECHMAP_REPLACE_ ( . OUT ( Y ) ,
. IN0 ( A [ 0 ] ) , . IN1 ( A [ 1 ] ) , . IN2 ( A [ 2 ] ) , . IN3 ( A [ 3 ] ) ) ;
end else begin
wire _ TECHMAP_FAIL_ = 1 ;
end
endgenerate
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endmodule
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module \ $ _ _ COUNT_ ( CE , CLK , OUT , POUT , RST , UP ) ;
input wire CE ;
input wire CLK ;
output reg OUT ;
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(* force_downto *)
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output reg [ WIDTH - 1 : 0 ] POUT ;
input wire RST ;
input wire UP ;
parameter COUNT_TO = 1 ;
parameter RESET_MODE = " RISING " ;
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parameter RESET_TO_MAX = 0 ;
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parameter HAS_POUT = 0 ;
parameter HAS_CE = 0 ;
parameter WIDTH = 8 ;
parameter DIRECTION = " DOWN " ;
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// If we have a DIRECTION other than DOWN fail .. . GP_COUNTx_ADV is not supported yet
if ( DIRECTION != " DOWN " ) begin
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initial begin
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$ display ( " ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?). " ) ;
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$ finish ;
end
end
// If counter is more than 14 bits wide , complain ( also shouldn't happen )
else if ( WIDTH > 14 ) begin
initial begin
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$ display ( " ERROR: \$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?). " ) ;
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$ finish ;
end
end
// If counter is more than 8 bits wide and has parallel output , we have a problem
else if ( WIDTH > 8 && HAS_POUT ) begin
initial begin
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$ display ( " ERROR: \$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?). " ) ;
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$ finish ;
end
end
// Looks like a legal counter ! Do something with it
else if ( WIDTH < = 8 ) begin
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if ( HAS_CE ) begin
wire ce_not ;
GP_INV ceinv (
. IN ( CE ) ,
. OUT ( ce_not )
) ;
GP_COUNT8_ADV # (
. COUNT_TO ( COUNT_TO ) ,
. RESET_MODE ( RESET_MODE ) ,
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. RESET_VALUE ( RESET_TO_MAX ? " COUNT_TO " : " ZERO " ) ,
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. CLKIN_DIVIDE ( 1 )
) _ TECHMAP_REPLACE_ (
. CLK ( CLK ) ,
. RST ( RST ) ,
. OUT ( OUT ) ,
. UP ( 1'b0 ) , // always count down for now
. KEEP ( ce_not ) ,
. POUT ( POUT )
) ;
end
else begin
GP_COUNT8 # (
. COUNT_TO ( COUNT_TO ) ,
. RESET_MODE ( RESET_MODE ) ,
. CLKIN_DIVIDE ( 1 )
) _ TECHMAP_REPLACE_ (
. CLK ( CLK ) ,
. RST ( RST ) ,
. OUT ( OUT ) ,
. POUT ( POUT )
) ;
end
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end
else begin
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if ( HAS_CE ) begin
wire ce_not ;
GP_INV ceinv (
. IN ( CE ) ,
. OUT ( ce_not )
) ;
GP_COUNT14_ADV # (
. COUNT_TO ( COUNT_TO ) ,
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. RESET_MODE ( RESET_TO_MAX ? " COUNT_TO " : " ZERO " ) ,
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. RESET_VALUE ( " COUNT_TO " ) ,
. CLKIN_DIVIDE ( 1 )
) _ TECHMAP_REPLACE_ (
. CLK ( CLK ) ,
. RST ( RST ) ,
. OUT ( OUT ) ,
. UP ( 1'b0 ) , // always count down for now
. KEEP ( ce_not ) ,
. POUT ( POUT )
) ;
end
else begin
GP_COUNT14 # (
. COUNT_TO ( COUNT_TO ) ,
. RESET_MODE ( RESET_MODE ) ,
. CLKIN_DIVIDE ( 1 )
) _ TECHMAP_REPLACE_ (
. CLK ( CLK ) ,
. RST ( RST ) ,
. OUT ( OUT )
) ;
end
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end
endmodule