2018-07-13 07:52:25 -05:00
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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2021-06-07 17:39:36 -05:00
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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2021-06-09 05:16:56 -05:00
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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2018-07-13 07:52:25 -05:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthEcp5Pass : public ScriptPass
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{
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SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
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2020-06-18 18:34:52 -05:00
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void on_register() override
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2020-05-04 13:44:00 -05:00
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{
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RTLIL::constpad["synth_ecp5.abc9.W"] = "300";
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}
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2020-06-18 18:34:52 -05:00
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void help() override
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2018-07-13 07:52:25 -05:00
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_ecp5 [options]\n");
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log("\n");
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log("This command runs synthesis for ECP5 FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -blif <file>\n");
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log(" write the design to the specified BLIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -edif <file>\n");
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log(" write the design to the specified EDIF file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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2020-04-14 09:51:23 -05:00
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log(" -dff\n");
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log(" run 'abc'/'abc9' with -dff option\n");
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log("\n");
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2018-07-13 07:52:25 -05:00
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log(" -retime\n");
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2019-12-30 14:11:45 -06:00
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log(" run 'abc' with '-dff -D 1' options\n");
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2018-07-13 07:52:25 -05:00
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log("\n");
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log(" -noccu2\n");
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log(" do not use CCU2 cells in output netlist\n");
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log("\n");
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log(" -nodffe\n");
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log(" do not use flipflops with CE in output netlist\n");
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log("\n");
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log(" -nobram\n");
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2019-07-16 15:44:55 -05:00
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log(" do not use block RAM cells in output netlist\n");
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2018-07-13 07:52:25 -05:00
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log("\n");
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2019-07-16 15:44:55 -05:00
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log(" -nolutram\n");
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log(" do not use LUT RAM cells in output netlist\n");
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2018-07-13 07:52:25 -05:00
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log("\n");
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2019-06-26 11:33:48 -05:00
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log(" -nowidelut\n");
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2018-07-13 07:52:25 -05:00
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log(" do not use PFU muxes to implement LUTs larger than LUT4s\n");
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log("\n");
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2019-12-07 07:04:36 -06:00
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log(" -asyncprld\n");
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2021-10-27 07:04:21 -05:00
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log(" use async PRLD mode to implement ALDFF (EXPERIMENTAL)\n");
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2019-12-07 07:04:36 -06:00
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log("\n");
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2018-07-13 07:52:25 -05:00
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log(" -abc2\n");
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log(" run two passes of 'abc' for slightly improved logic density\n");
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log("\n");
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2019-06-14 06:02:12 -05:00
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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2018-07-13 07:52:25 -05:00
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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log("\n");
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2019-08-08 09:18:59 -05:00
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log(" -nodsp\n");
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log(" do not map multipliers to MULT18X18D\n");
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2019-07-08 09:40:12 -05:00
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log("\n");
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2022-06-02 10:15:28 -05:00
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log(" -no-rw-check\n");
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log(" marks all recognized read ports as \"return don't-care value on\n");
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log(" read/write collision\" (same result as setting the no_rw_check\n");
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log(" attribute on all memories).\n");
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log("\n");
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2018-07-13 07:52:25 -05:00
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, blif_file, edif_file, json_file;
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2022-06-02 10:15:28 -05:00
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bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr, no_rw_check;
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2018-07-13 07:52:25 -05:00
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2020-06-18 18:34:52 -05:00
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void clear_flags() override
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2018-07-13 07:52:25 -05:00
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{
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top_opt = "-auto-top";
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blif_file = "";
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edif_file = "";
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json_file = "";
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noccu2 = false;
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nodffe = false;
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nobram = false;
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2019-07-16 15:44:55 -05:00
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nolutram = false;
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2019-06-26 11:33:48 -05:00
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nowidelut = false;
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2019-12-07 07:04:36 -06:00
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asyncprld = false;
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2018-07-13 07:52:25 -05:00
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flatten = true;
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2020-04-14 09:51:23 -05:00
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dff = false;
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2018-07-13 07:52:25 -05:00
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retime = false;
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abc2 = false;
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vpr = false;
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2019-06-14 06:02:12 -05:00
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abc9 = false;
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2019-08-08 09:18:59 -05:00
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nodsp = false;
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2022-06-02 10:15:28 -05:00
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no_rw_check = false;
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2018-07-13 07:52:25 -05:00
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}
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2020-06-18 18:34:52 -05:00
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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2018-07-13 07:52:25 -05:00
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-blif" && argidx+1 < args.size()) {
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blif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-edif" && argidx+1 < args.size()) {
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edif_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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2020-04-14 09:51:23 -05:00
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if (args[argidx] == "-dff") {
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dff = true;
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continue;
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}
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2018-07-13 07:52:25 -05:00
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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}
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if (args[argidx] == "-noccu2") {
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noccu2 = true;
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continue;
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}
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if (args[argidx] == "-nodffe") {
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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}
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2019-12-07 07:04:36 -06:00
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if (args[argidx] == "-asyncprld") {
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asyncprld = true;
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continue;
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}
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2019-07-16 15:44:55 -05:00
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if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
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nolutram = true;
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2018-07-13 07:52:25 -05:00
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continue;
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}
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2019-07-16 15:44:55 -05:00
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if (args[argidx] == "-nowidelut" || /*deprecated alias*/ args[argidx] == "-nomux") {
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2019-06-26 11:33:48 -05:00
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nowidelut = true;
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2018-07-16 07:33:13 -05:00
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continue;
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}
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2018-07-13 07:52:25 -05:00
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if (args[argidx] == "-abc2") {
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abc2 = true;
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continue;
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}
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if (args[argidx] == "-vpr") {
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vpr = true;
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continue;
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}
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2019-06-14 06:02:12 -05:00
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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2019-08-08 09:18:59 -05:00
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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2019-07-08 09:40:12 -05:00
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continue;
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}
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2022-06-02 10:15:28 -05:00
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if (args[argidx] == "-no-rw-check") {
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no_rw_check = true;
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continue;
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}
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2018-07-13 07:52:25 -05:00
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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2018-12-07 13:14:07 -06:00
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log_cmd_error("This command only operates on fully selected designs!\n");
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2018-07-13 07:52:25 -05:00
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2019-07-10 14:47:48 -05:00
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if (abc9 && retime)
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log_cmd_error("-retime option not currently compatible with -abc9!\n");
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2018-07-13 07:52:25 -05:00
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log_header(design, "Executing SYNTH_ECP5 pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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2020-06-18 18:34:52 -05:00
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void script() override
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2018-07-13 07:52:25 -05:00
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{
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2022-06-02 10:15:28 -05:00
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std::string no_rw_check_opt = "";
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if (no_rw_check)
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no_rw_check_opt = " -no-rw-check";
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if (help_mode)
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no_rw_check_opt = " [-no-rw-check]";
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2018-07-13 07:52:25 -05:00
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if (check_label("begin"))
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{
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2020-02-12 13:30:37 -06:00
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run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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2018-07-13 07:52:25 -05:00
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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2019-09-26 12:45:14 -05:00
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if (check_label("coarse"))
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2018-07-13 07:52:25 -05:00
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{
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run("proc");
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2019-09-26 12:45:14 -05:00
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if (flatten || help_mode)
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run("flatten");
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2018-07-13 07:52:25 -05:00
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run("tribuf -logic");
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run("deminout");
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2019-07-08 09:40:12 -05:00
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run("opt_expr");
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run("opt_clean");
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run("check");
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2020-07-20 16:19:51 -05:00
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run("opt -nodffe -nosdff");
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run("fsm");
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2019-07-08 09:40:12 -05:00
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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2019-08-08 09:18:59 -05:00
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if (!nodsp) {
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2019-09-26 12:45:14 -05:00
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run("techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=$__MUL18X18", "(unless -nodsp)");
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2019-08-08 09:18:59 -05:00
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run("chtype -set $mul t:$__soft_mul", "(unless -nodsp)");
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2019-07-08 09:40:12 -05:00
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}
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run("alumacc");
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run("opt");
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2022-06-02 10:15:28 -05:00
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run("memory -nomap" + no_rw_check_opt);
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2019-07-08 09:40:12 -05:00
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run("opt_clean");
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2018-07-13 07:52:25 -05:00
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}
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2022-02-07 20:52:16 -06:00
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if (check_label("map_ram"))
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2018-07-13 07:52:25 -05:00
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{
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2022-02-07 20:52:16 -06:00
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std::string args = "";
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if (nobram)
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args += " -no-auto-block";
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if (nolutram)
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args += " -no-auto-distributed";
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if (help_mode)
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args += " [-no-auto-block] [-no-auto-distributed]";
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run("memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
|
|
|
run("techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v");
|
2018-07-13 07:52:25 -05:00
|
|
|
}
|
|
|
|
|
2019-07-11 05:56:59 -05:00
|
|
|
if (check_label("map_ffram"))
|
2018-07-13 07:52:25 -05:00
|
|
|
{
|
|
|
|
run("opt -fast -mux_undef -undriven -fine");
|
2022-02-07 20:52:16 -06:00
|
|
|
run("memory_map");
|
2018-07-13 07:52:25 -05:00
|
|
|
run("opt -undriven -fine");
|
2019-07-11 05:56:59 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("map_gates"))
|
|
|
|
{
|
2018-07-13 08:46:12 -05:00
|
|
|
if (noccu2)
|
2018-07-13 07:52:25 -05:00
|
|
|
run("techmap");
|
|
|
|
else
|
|
|
|
run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
|
2020-02-05 20:39:01 -06:00
|
|
|
run("opt -fast");
|
2018-07-13 07:52:25 -05:00
|
|
|
if (retime || help_mode)
|
2019-12-30 14:09:53 -06:00
|
|
|
run("abc -dff -D 1", "(only if -retime)");
|
2018-07-13 07:52:25 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("map_ffs"))
|
|
|
|
{
|
2018-07-14 08:54:30 -05:00
|
|
|
run("opt_clean");
|
2020-07-20 16:19:51 -05:00
|
|
|
std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
|
|
|
|
if (help_mode) {
|
|
|
|
dfflegalize_args += " [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r]";
|
|
|
|
} else if (!nodffe) {
|
|
|
|
dfflegalize_args += " -cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r";
|
|
|
|
}
|
|
|
|
if (help_mode) {
|
2021-10-27 07:04:21 -05:00
|
|
|
dfflegalize_args += " [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]";
|
2020-07-20 16:19:51 -05:00
|
|
|
} else if (asyncprld) {
|
2021-10-27 07:04:21 -05:00
|
|
|
dfflegalize_args += " -cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x";
|
|
|
|
} else {
|
|
|
|
dfflegalize_args += " -cell $_DLATCH_?_ x";
|
2020-07-20 16:19:51 -05:00
|
|
|
}
|
2021-10-27 07:04:21 -05:00
|
|
|
run("dfflegalize" + dfflegalize_args, "($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)");
|
2020-04-14 09:51:23 -05:00
|
|
|
if ((abc9 && dff) || help_mode)
|
2021-09-09 12:05:55 -05:00
|
|
|
run("zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*", "(only if -abc9 and -dff)");
|
2021-10-27 07:04:21 -05:00
|
|
|
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
|
2019-04-30 07:46:12 -05:00
|
|
|
run("opt_expr -undriven -mux_undef");
|
2018-07-13 07:52:25 -05:00
|
|
|
run("simplemap");
|
2019-08-27 07:07:06 -05:00
|
|
|
run("ecp5_gsr");
|
2019-10-10 09:58:31 -05:00
|
|
|
run("attrmvcp -copy -attr syn_useioff");
|
2019-08-27 07:07:06 -05:00
|
|
|
run("opt_clean");
|
2018-07-13 07:52:25 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("map_luts"))
|
|
|
|
{
|
2020-05-13 16:16:42 -05:00
|
|
|
if (abc2 || help_mode)
|
2018-07-13 07:52:25 -05:00
|
|
|
run("abc", " (only if -abc2)");
|
2020-05-13 16:42:18 -05:00
|
|
|
if (!asyncprld || help_mode)
|
|
|
|
run("techmap -map +/ecp5/latches_map.v", "(skip if -asyncprld)");
|
2019-08-20 20:59:03 -05:00
|
|
|
|
2019-06-14 06:02:12 -05:00
|
|
|
if (abc9) {
|
2020-05-04 13:44:00 -05:00
|
|
|
std::string abc9_opts;
|
|
|
|
if (nowidelut)
|
|
|
|
abc9_opts += " -maxlut 4";
|
|
|
|
std::string k = "synth_ecp5.abc9.W";
|
|
|
|
if (active_design && active_design->scratchpad.count(k))
|
|
|
|
abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
|
|
|
|
else
|
|
|
|
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
|
2019-06-26 12:23:29 -05:00
|
|
|
if (nowidelut)
|
2020-05-13 16:12:06 -05:00
|
|
|
abc9_opts += " -maxlut 4";
|
2020-04-14 09:51:23 -05:00
|
|
|
if (dff)
|
2020-05-13 16:12:06 -05:00
|
|
|
abc9_opts += " -dff";
|
|
|
|
run("abc9" + abc9_opts);
|
2019-06-14 06:02:12 -05:00
|
|
|
} else {
|
2020-04-14 09:51:23 -05:00
|
|
|
std::string abc_args = " -dress";
|
2019-06-26 12:04:01 -05:00
|
|
|
if (nowidelut)
|
2020-04-14 09:51:23 -05:00
|
|
|
abc_args += " -lut 4";
|
2019-06-14 06:02:12 -05:00
|
|
|
else
|
2020-04-14 09:51:23 -05:00
|
|
|
abc_args += " -lut 4:7";
|
|
|
|
if (dff)
|
|
|
|
abc_args += " -dff";
|
|
|
|
run("abc" + abc_args);
|
2019-06-14 06:02:12 -05:00
|
|
|
}
|
2018-07-13 07:52:25 -05:00
|
|
|
run("clean");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("map_cells"))
|
|
|
|
{
|
2020-04-14 09:51:23 -05:00
|
|
|
if (help_mode)
|
|
|
|
run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
|
|
|
|
else if (!vpr)
|
|
|
|
run("techmap -map +/ecp5/cells_map.v");
|
2020-02-03 07:57:17 -06:00
|
|
|
run("opt_lut_ins -tech ecp5");
|
2018-07-13 07:52:25 -05:00
|
|
|
run("clean");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("check"))
|
|
|
|
{
|
2019-11-15 15:03:11 -06:00
|
|
|
run("autoname");
|
2018-07-13 07:52:25 -05:00
|
|
|
run("hierarchy -check");
|
|
|
|
run("stat");
|
|
|
|
run("check -noinit");
|
2021-03-17 07:16:53 -05:00
|
|
|
run("blackbox =A:whitebox");
|
2018-07-13 07:52:25 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("blif"))
|
|
|
|
{
|
|
|
|
if (!blif_file.empty() || help_mode) {
|
|
|
|
if (vpr || help_mode) {
|
|
|
|
run(stringf("opt_clean -purge"),
|
|
|
|
" (vpr mode)");
|
|
|
|
run(stringf("write_blif -attr -cname -conn -param %s",
|
|
|
|
help_mode ? "<file-name>" : blif_file.c_str()),
|
|
|
|
" (vpr mode)");
|
|
|
|
}
|
|
|
|
if (!vpr)
|
|
|
|
run(stringf("write_blif -gates -attr -param %s",
|
|
|
|
help_mode ? "<file-name>" : blif_file.c_str()),
|
|
|
|
" (non-vpr mode)");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("edif"))
|
|
|
|
{
|
|
|
|
if (!edif_file.empty() || help_mode)
|
|
|
|
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_label("json"))
|
|
|
|
{
|
|
|
|
if (!json_file.empty() || help_mode)
|
|
|
|
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} SynthEcp5Pass;
|
|
|
|
|
|
|
|
PRIVATE_NAMESPACE_END
|