Commit Graph

2309 Commits

Author SHA1 Message Date
Jean-Paul Chaput 5cba995549 In cumulus/plugins.chip.powerplane, check for too-narrow power contacts. 2021-04-24 12:58:22 +02:00
Jean-Paul Chaput 8d54a9cc29 In Etesian::Placement, reduce the number of warnings in case of misaligned block. 2021-04-24 12:56:32 +02:00
Jean-Paul Chaput 496cc00304 In Katana, Adjust the moveUp cases in SegmentFsm/Manipulator.
* Change: In SegmentFsm::_slackenLocal(), in the Minimize state, when
    the segment is fully blocked *and* has *lot* of candidate tracks,
    that means that it is up against a *massive* blockage (i.e. a macro
    block). In that case, try to move up (to go *over* it).
      Previous behavior was to go straight to Inimplemented state.
* Change: In SegmentFsm::_slackenGlobal(), manage fully blocked
    global segments. But finally, this configuration didn't arise.
* Change: In Manipulator::moveUp(), restore the management of the
    AllowLocalMoveUp flag, to be able to move up local segments
    (needed by SegmentFsm::_slackenLocal()).
2021-04-24 12:56:16 +02:00
Jean-Paul Chaput 79f5b3db08 In AutoSegment::canMoveUp(), increase to 2 the added penalty under FlexLib. 2021-04-24 12:55:47 +02:00
Jean-Paul Chaput decc4745d2 Add a RoutingLayerGauge.setType() and export to Python (finally unused). 2021-04-24 12:55:17 +02:00
Jean-Paul Chaput 0640586cbc In CRL::VstDriver, name-mangle file names too with option UniquifyUpperCase.
* Bug: In CRL::vstDriver(), when upper case names are uniquified, including
    components, the associated model filename must also be mangled.
2021-04-22 15:14:06 +02:00
Jean-Paul Chaput 03a52977d3 Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel 2021-04-21 17:01:55 +02:00
Jean-Paul Chaput 37f311ac7d Don't remembers what thoses do, but don't want to loose them either. 2021-04-21 17:00:48 +02:00
Luke Kenneth Casson Leighton 7ba68a0718 whoops, sorry... 2021-04-21 14:30:58 +00:00
Luke Kenneth Casson Leighton 8932bcf7bc add BigVia.AllowAllExpand to all corona pads.
this is already done elsewhere BigVia is used.
no reason not to also use it in corona
2021-04-21 14:07:29 +00:00
Jean-Paul Chaput d10961b585 Put the clock tree connecting wires farther apart from the corona border.
* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
    from the corona border to the root of the HTree, the horizontal
    wire at the top was too close from the border causing a minimal
    spacing error in the DRC. Now put two tracks of distance.
2021-04-21 14:16:53 +02:00
Jean-Paul Chaput f2f5f687d0 Shrink macro block external pins.
* Bug: In cumulus/plugins.macro.Macro, external west/east segments where
    slightly too long and conflicted with the METAL2 blockage.
2021-04-21 14:16:26 +02:00
Jean-Paul Chaput f4514cecf3 Use Track::repair() to solve overlaps.
* New: In Track::repair(), the gapset was used to *close* same-net gaps
   is now alos used to restore minimal spacing between different nets.
   Seems to be not fully working yet.
2021-04-21 13:51:33 +02:00
Jean-Paul Chaput a05bd81bab Complete reorganization of where the routing stage is stored in Katana.
* In KatanaEngine:
    - Former situation:
        Each RoutingEvent did store the routing stage it was in. And it
        was misnamed "mode".
    - New organization:
        The routing stage is stored in KatanaEngine itself. It can be
	accessed through a proxy in Session.
* Change: In DataNegociate::update(), when in Realign stage and computing
    non-preferred perpnadicular routing *do not* expand of one pitch
    outside the RoutingPad range.
2021-04-21 13:51:08 +02:00
Jean-Paul Chaput 493ed1ea11 In AutoSegment::canMoveUp(), adjust balance for FlexLib M2/M4.
* Change: In AutoSegment::canMoveUp(), hard code for FlexLib a track
    reserve of one when trying to move up.
      In FlexLib, the router promotes too easily METAL2 towards METAL4,
    clogging the higher level. So we end up with the METAL2 level
    under-saturated and the METAL4 over saturated, leading to routing
    failures.
      Now we assume that there is "one track less available" in METAL4.
      As for now, solves the problem for LibreSOC.
2021-04-21 13:49:41 +02:00
Jean-Paul Chaput ab908b8c44 Issue an early warning for offgrid coordinates in GdsParser. 2021-04-19 14:29:23 +02:00
Jean-Paul Chaput cd4f797831 Export terminal of I/O pads at chip level. 2021-04-19 14:26:29 +02:00
Jean-Paul Chaput 3b6b588a74 Manage pads for external components in CRL::GdsParser.
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
    for Net external components. Also delete the original components
    after creating the copy in the right Net.
      So now the PLL terminals are correctly seen.
2021-04-18 20:37:19 +02:00
Jean-Paul Chaput 7d1e1f8c44 Adjust again the interface of the SRAM block (METAL2 stick out more). 2021-04-18 20:36:57 +02:00
Jean-Paul Chaput 2084a3bde2 Bad computation of the track axis for fixed in NetBuilderHV::_do_xG_1PinM2().
* Bug: In NetBuilderHV::_do_xG_1PinM2(), for METAL2 pins on the EAST
    side, we were computing the track from the XMax position of the
    GCell. Now, with complete discoupling of the routing pitches and
    GCell size, this is most of the time false.
      Replace with a true computation of the last track of routing
    area.
2021-04-18 20:36:44 +02:00
Jean-Paul Chaput 2019fa25d7 Fix crash when getting the free interval around a TrackSegment.
* Bug: In TrackSegment::getFreeInterval(), if, for whatever reason,
    a discrepency happens between the TrackSegment and the Track,
    that is the _track fields point to a *wrong* Track. Then the
    index lookup will fail (Track::npos), so return an all-span
    interval instead of trying to expand it and crash (out of
    bound).
2021-04-18 20:36:20 +02:00
Jean-Paul Chaput 444cc777e5 Fix topological bug in NetBuilderHV::_do_xG_1PinM2().
* Bug: In NetBuilderHV::_do_xG_1PinM2(), when the M2 pin is on the *east*
    side and there are three globals, we must swap htee1 & htee2.
      Otherwise, we the SW/NE contacts do not have the right numbers
    of free segments attach.
* New: In AnabaticEngine::cleanupGlobal(), check that no global component
    is left behind, sure sign that the global to detailed building went
    wrong.
2021-04-17 13:03:15 +02:00
Jean-Paul Chaput 445f5161da Increase again blockages area over SRAMs blocks. 2021-04-17 12:56:40 +02:00
Jean-Paul Chaput b0cfe8fc82 Fix bad spacing of the rightmost power lines (just a sign error). 2021-04-17 12:54:49 +02:00
Luke Kenneth Casson Leighton aeb9d7d4e5 blif2vst.py naming of components needs to be munged
https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/36

Signed-off-by: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2021-04-16 12:41:39 +00:00
Luke Kenneth Casson Leighton 628ff1ae06 correct direction of core-to-corona gpio pad connections for Net.Direction.IN
cumulus/src/plugins/alpha/core2chip/core2chip.py

Signed-off-by: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
2021-04-16 12:19:41 +00:00
Jean-Paul Chaput cc2137ec4f Check that the core is wide enough to accomodate at least one middle power line. 2021-04-16 11:43:22 +02:00
Jean-Paul Chaput 9800c0ad3d Correct my botched patch on Etesian::HFNS buffer vs. net naming. 2021-04-16 10:31:49 +02:00
Jean-Paul Chaput 8279e76070 In Etesian, set correct direction for buffereds HFNS nets.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically
    created in the IN direction, which is obviously wrong for the driver.
      Now Slice::raddTransPlug() accept a third argument stating if we are
    creating a driver or a sink. Direction of the net is now combining
    and can be IN, OUT or sometimes INOUT.
      The VHDL files where reflecting that problem and made GHDL choke.
* Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_"
    so it doesn't clash with the signal name in VHDL.
2021-04-16 00:05:04 +02:00
Jean-Paul Chaput 813d0860fd In Etesian::Placement, ensure that the tie in holes are pitcheds.
* Bug: In Etesian::Placement::Slice::fillHole(), do not use the xmin
    previous bound, but pitch it (by excess). Insert ties *only* if
    they completely fit in the free space.
      This bug was showing *between* two SRAMs side-by-side, a column
    of tie was inserted...
2021-04-15 23:55:29 +02:00
Jean-Paul Chaput 7f41cd73c7 In EtesianEngine::toColoquinte(), increase the buf_x8 size to solve DRC/LUP. 2021-04-15 23:50:54 +02:00
Jean-Paul Chaput 20efd75a32 More accurate detection of zero-length segments.in AutoSegment::canReduce(). 2021-04-15 23:47:21 +02:00
Jean-Paul Chaput 95713ac66b Align power lines on QuadTree leaf area centers (X).
* Bug: In cumulus/plugins.block.block.py, always import Python modules
    using the exact same path. Otherwise the module may get imported
    twice and static variables are duplicated, generating a big mess.
      This was causing problem for the LUT in macro.py, and got SRAMs
    blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
    a "place holder" instance over a given area to prevent the placer
    from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
    toXPitch() and toYSlice() methods from spare in order to share
    them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
    the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
    doChipFloorplan() to doConnectCore(), this is to delay the call
    until *after* the spare QuadTree has been created and we can
    align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
    spare QuadTree has been created, align the power lines on the
    X center of the leaf areas. This is a cheap way to avoid DRC
    errors between the power BigVias and the wires from the various
    clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
    SRAMs. The blockage areas are slightly too narrow. We enlarge
    them by one pitch.
2021-04-15 23:44:19 +02:00
Jean-Paul Chaput dd28bbba7a Comment out debug messages in GdsDriver & GdsParser. 2021-04-15 23:22:07 +02:00
Jean-Paul Chaput 2002282483 Add a zero-length segment compaction stage in Anabatic DTOR.
* New: In AnabaticEngine::_gutAnabatic(), perform progessive compaction
    of segment of null length.
      CAUTION: Reduced segments *may* not be null length segments.
               They are "less or equal" than one perpandicular pitch and
	       can have their layer put into the perpandicular one.
                 They non-null one *must* be excluded for the compaction.
      Null segments are compacted starting from the one connecteds to
   non-null length segments. This is to avoid the compaction starting
   in the middle of a whole set of zero-segments that will block further
   compaction.
     This behavior was causing "zero-length" segment on orphaned layers
   that were causing minumal area DRC errors.
* Change: AutoSegment::canReduce() is modified so it now takes a flag
    argument to tell it to look for collapisble zero-length segments.
* New: AutoSegment::getNonReduceds(): returns the number of non-zero
    length segments connecteds to the current one.
* Change: In AutoSegment::reduceDoglegLayer(), use the perpandicular
    width of the routing layer instead of the regular (parallel) one.
      This was causing DRC errors.
2021-04-12 23:50:25 +02:00
Jean-Paul Chaput 2f24c05a72 Fix bug in Track::repair(), select the right segment to extend. 2021-04-12 23:34:55 +02:00
Jean-Paul Chaput a66da90446 Never reduce METAL2 short wires to METAL1.
* Change: In AutoSegment::canReduce(), no longer allow short METAL2
    connected only to VIA12 to be reduced in METAL1, as we do not
    control the METAL1 level of layers. This problem started to
    show when connecting to diodes (antenna).
      Should get rid of METAL1 DRC violations.
2021-04-10 19:51:50 +02:00
Jean-Paul Chaput 81fffb9d0a Add a new Track finishing stage: close short gaps of same nets wires.
* New: In Track::repair(), short gaps between segments of the same
    nets where occuring and being not detected. This was causing
    DRC minimal distance violations. Now, fuse the segments when
    they are too close. Done by extenting the duSource of the
    rightmost one to the leftlost one.
       Create ancillary class GapSet to manage the gaps of the
    various segment of the same net.
2021-04-10 19:51:19 +02:00
Jean-Paul Chaput d3ee38b01e Forgot to update root clocktree wiring for block-only routing. 2021-04-10 19:41:30 +02:00
Jean-Paul Chaput 3276950ec4 Prefix all Cell from a GDS file with "gds_" to avoid cell overload.
* Bug: In CRL::GdsParser, the PLL was using copies of the standard cell
    with the same name. And unfortunately, they where found *before*
    the FlexLib one when using DataBase::getCell(). As their I/O where
    wrong it was leading to a massive netlist connexion corruption in
    blif2vst.
      To avoid that, any Cell created by the GDS parser is now prefixed
    by "gds_".
* Change: In CRL::GdsStream CTOR, report when the file cannot be opened
    instead of saying that the GDS file is corrupted (misleading).
2021-04-09 13:55:08 +02:00
Jean-Paul Chaput 3eb3f52bc8 Refining check in AutoSegment::isMiddleStack().
* Change: In AutoSegment::isMiddleStack(), reject configurations where
    we have a Tee in the same direction as the segment. That is, (HTee + H)
    or (VTee + V). It is unlikely that the two segments of the tee will
    be of null size.
2021-04-09 13:54:46 +02:00
Jean-Paul Chaput 2a1f014491 Added a new post-routing stage "realign" in Katana.
When a segment is placed only once (which is to say it is nerver ripped
up) it can sometimes end-up in a non-optimal place. We now add a stage
in Katana where each segment is "re-placed" in order to maximise
alignment on it's neighbor. This is a new stage added to both
RoutingEvent and NegociateWidow. Segments are replaced *only* in free
space, they will not ripup *other* segments, except for their own
perpandiculars. We exclude from re-placement globals (unlikely to move)
and segment that have reduced perpandiculars which *must* not be elongated
and potentially raised.
  Add a new katana setting to enable/disable the realign stage (enabled
by default:
    - "katana.runRealignStage" ( = True )
2021-04-08 15:10:14 +02:00
Jean-Paul Chaput 4b6da7bde9 Suppress uneeded debug output in Cumulus/plugins.chip.pads. 2021-04-08 15:09:41 +02:00
Jean-Paul Chaput 31d6a45702 In Cumulus/plugins.block.iospecs, add IoPin.START and END to auto-load specs.
Contributed by LKCL.
2021-04-08 11:22:12 +02:00
Jean-Paul Chaput 556c38e4b9 Bug in spares.py, "rtag", the root was repeated in each level. 2021-04-07 14:51:32 +02:00
Jean-Paul Chaput df4201e1fe Manage a minimum spacing between I/O pads at chip level.
* Change: In Cumulus/plupins.chip.pads.Side, in some case (LibreSOCIOPads),
    when not put side by side, the I/O pads must be separated by a
    minimal distance.
      Introduce the new configuration parameter:
        cfg.chip.minPadSpacing
      Disabled if zero or non-defined.
      Fix NWELL DRC errors for TSMC.
2021-04-07 14:51:16 +02:00
Jean-Paul Chaput a2525f2260 More accurate detection of small metal srips for minimum area.
* Change: In AutoSegment::isMiddlestack(), we where previously only
    detecting (turn+turn) or (turn+terminal) topologies. This was
    too restrictive. Added (terminal+XTee) when the tee is perpandicular
    to the segment, for example horizontal + VTee.
      Fix minimal area DRC error in METAL2 for TSMC.
2021-04-07 14:50:42 +02:00
Jean-Paul Chaput e6f18a95d3 Fix vector mapping in VHDL portmap. one/zero names in BlifParser.
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
    are part of a vector, but *not* in the "downto" direction,
    unvectorize anyway. In the component declarations, vectors are
    always in "downto" order, so they must also be mapped in that
    order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
    signal names different from instance names for VHDL compliance.
    This is complementary to what is done in blif2vst.
      No completely satisfied with that. Should find a more generic
    way to do it in the future.
2021-04-06 18:19:16 +02:00
Jean-Paul Chaput ec3c22547a Bug fixes in the VST/VHDL driver coupled with BlifParser.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
    the external status of the former Net. When a Net::merge() is
    performed, we must keep track of whether the merged (destroyed)
    one was external and keep that information.
      Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
    virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
    search of the net name in *internal* aliases. Otherwise only the
    aliases tagged as *external* will be searched.
      It was a bug that, when looking for a Plug master net by name
    we got an homonymous internal net. In that case we must only
    look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
    unvectorize it, like when it is non-contiguous (we use the
    isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
    a flag UniquifyUpperCase to uniquify the names in uppercases.
    In case of a clash with the same name in lowercase.
      Prepend 'u' before all previously uppercased letter. For
    example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
      The Catalog flags is exported to Python for use by the blif2vst
    script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
    a new gate each time it is called instead of making just one for
    each Model. This way, if two outside nets are connected to one
    or zero they do not get merged (should work, but will be less
    clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
    master net in the instances models (by name), limit the search
    to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
    two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
    (i.e. components) with 'cmpt_' to avoid clash names with signals
    in VHDL.
2021-04-05 23:53:44 +02:00
Jean-Paul Chaput 08d1db5dd6 Rewrite support for minimum area metal wires (stacked VIAs).
We use the segments extensions (dxTarget & dyTarget) to enlarge if
needed the segments. This new implementation is completely at
Anabatic level and should not be seen (i.e. managed) at Katana level.

* Change: In AutoHorizontal & AutoVertical, change the semantic of
    getSourceU() and getTargetU(). formerly they where the end
    position of the segment (with extension included), now they
    gives the position of the anchor contacts, that is the axis
    of the perpandiculars.
* New: AutoSegment::getLength() is still a proxy toward the
     Segment::getLength() which returns the length of segment with
     dxSource & dxTarget. We introduce a getAnchoredlength()
     which returns the length between the centers of the S/T
     anchors. That is axis to axis.
       This is this length which is now used througout Anabatic.
* New: In AutoSegment::_extentionCaps, add a fourth item to hold
    the segment minimal length (to respect minimal area given
    the wire width).
* New: In AutoSegment::getExtensionCap(), if the segment has
    a non-zero S/T extension, returns it instead of the S/T
    contact extension *if it is greated*. The check of the
    extension can be disabled by the Flag::NoSegExt flag.
* Change: In AutoSegment::isMiddleStack(), security check on
    the presence of source and targets. More accurate detection
    of perpandicular in "same layer" with a non-zero length,
    So the area is OK, even with a short segment.
* New: AutoSegment::expandToMinLength(), check if a segment is
    under the minimal length and expand it if need be by playing
    with the dxTarget & dxSource. Tag minimal segments with the
    AutoSegment::SegAtMinArea flag. Also try to keep the segment
    *inside* it's former (supposedly wider) interval.
* New: AutoSegment::unexpandToMinLength(), to be called on a
    formerly minimal sized segment which as grown up. Reset
    it's S/T extensions to zero and unset the flag SegAtMinArea.
* Change: In AutoHorizontal::updateOrient(), when the extension
    are non-zero, also swap them if needed, to keep the exact
    footprint of the segment.
* New: In AutoSegment::revalidate(), check that the segment
    respect the minimal length (area), and expand it if needed.
      Conversely, if the segment has grown up from a minimal
    length state, reset it's extensions to zero.
* Change: In Anabatic::Session::revalidate(), invalidateds
    segments are now sorted in such a way that the "middle stack"
    ones are revalidateds last. Not recall 100% why...
* New: In Katana::TrackCost, add a computation of the free interval
    length we are into (if any). Not used yet, keep it for future
    use.
* Change: In KatanaEngine::finalizeLayout(), remove the call to
    segments minimum area protection. It is now obsoleted by the
    new implementation in Anabatic.
* Change: In Track::check(), call the minimum size/area checker
    Track::checkMinArea().
2021-04-05 00:01:54 +02:00