Protecting clusters of sinks is not enough. There can be very long
wires that far exceed the protection capacity of one diode. Instead
of putting a bunch of diodes near the sinks, we choose to put them
regularly along the interconncting wires.
With this approach we are down to 7 antenna violations on LibreSOC
LS180 test chip.
This will get less good results on arlet6502 & ao6800 because of the
core being a long way from the I/O pads. Should create jumpers on thoses,
but it is for later.
* Change: In Track::addOverlapCost(), in some configuration, we can
have two overlapping short segments that can *both* be realigned.
But they prevent that because we account their shared length on
the track.
So now, in realign mode only, do not account same-net shared
length if the segment length is less than *two perpandicular pitches*.
This helps the antenna protection by making the diode connected
directly to METAL2 long stripes, and not keeping them isolated.
* In cumulus/plugins.block.Block.{place,doPnr}(), reorder the
feed insertion and spare buffer deletion call. Formerly, we
were :
1. Creating spare buffersa (Python).
2. Placing (C++)
3. Adding feeds (EtesianEngine::toHurricane() call) (C++).
4. Removing unused spare buffers (Python).
So, step 4 was *not* informing the C++ placement data-structure
created at step 3 of the change. Resulting in occurrences using
deleted Entities (Instance).
Now we swap step 3. and 4. so toHurricane() is called *after*
any Python managed change is done.
Ideally, what we should implement is a way for Python to inform
the C++ data-structure. No real problem here, but time...
* In Etesian::Slice::createDiodeUnder(), delete the Instance *after*
removing the tile referring it. This was working, unless we
active the debug mode which tries to print the Tile's instance.
* In EtesianEngine::place(), no longer call toHurricane() at the
end of the placement. Must now be done as a separate step.
Exported to Python interface.
This fix is related to the spare buffer removal memory
corruption
* Change: In Katana::Track::addOverlapCost(), if an overlaping segment
is owned by the net *and* is the one we want to insert, do not take
it into account in the shared length.
This case never occured before we introduced the "realign" stage,
as a to be inserted segment, was, by definition, not already
inserted in a track. But in the realign stage, it is. So we should
not account it when computing the insertion cost in the track it
is already in. This was preventing short segments (less than a
pitch) to be correctly re-aligned.
And, as a side effect, preventing the antenna/diodes to work as
intended (diode connected at METAL3 layer while the antenna occur
at METAL2 layer).
* Change: In cumulus/plugins.block.configuration.Configuration.save()
and cumulus/plugins.chip.Chip.save(), according to the kind of
routing gauge we are using (symbolic or real), either recursively
save all the layouts (AP symbolic files) or only the top-level
GDSII (which embed all the hierarchy) one.
First part of the antenna effect protection : diode insertions.
Anabatic::antennaProtect(Net*) and it's supporting infrastructure
has been rewritten & simplificated. Must be used in conjuction
with the "Flexlib" bloat model of Etesian. A cursory description
of the algorithm has been added in the source file.
* New: GCell::hasNet() to tell if net is going through a GCell,
either as a straigth wire or has a local GContact (turn,
branch, terminal).
* New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
flexlib uses. It is derived from "nsxlib".
To have enough space to insert all the wanted diodes, we
enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
This is an empiric finding, Yosys seems very fond of thoses
gates and we often see them underneath area where no space
was available to put a diode... May need some more fine grained
analysis.
* Bug: In cumulus/plugins.chip.pads, we were connecting the ground and
power supplies to all the horizontal wires in the corona ring.
But, when there are more than one and especially at the outer
border of the pad, the vertical connecting wire will create
various shorts over the pad.
Now we connect only to the innermost horizontal wire only.
Had to chech if the core side of the pad is north or south.
* New: In CRL::PyCatalog, add the second parameter "add" to getState()
so we can request the creation of the state if needed.
* New: In CRL::PyCatalogState, export setCell() and setInMemory() methods.
* Bug: In CRL::Subckt::createModel(), when a cell has a State entry in
the catalog, also check that it really has a Cell loaded in memory.
If not, throw an exception (and do not crash).
* Change: In SegmentFsm::_slackenLocal(), in the Minimize state, when
the segment is fully blocked *and* has *lot* of candidate tracks,
that means that it is up against a *massive* blockage (i.e. a macro
block). In that case, try to move up (to go *over* it).
Previous behavior was to go straight to Inimplemented state.
* Change: In SegmentFsm::_slackenGlobal(), manage fully blocked
global segments. But finally, this configuration didn't arise.
* Change: In Manipulator::moveUp(), restore the management of the
AllowLocalMoveUp flag, to be able to move up local segments
(needed by SegmentFsm::_slackenLocal()).
* Bug: In cumulus/plugins.chip.powerplane, while building the connexion
from the corona border to the root of the HTree, the horizontal
wire at the top was too close from the border causing a minimal
spacing error in the DRC. Now put two tracks of distance.
* New: In Track::repair(), the gapset was used to *close* same-net gaps
is now alos used to restore minimal spacing between different nets.
Seems to be not fully working yet.
* In KatanaEngine:
- Former situation:
Each RoutingEvent did store the routing stage it was in. And it
was misnamed "mode".
- New organization:
The routing stage is stored in KatanaEngine itself. It can be
accessed through a proxy in Session.
* Change: In DataNegociate::update(), when in Realign stage and computing
non-preferred perpnadicular routing *do not* expand of one pitch
outside the RoutingPad range.
* Change: In AutoSegment::canMoveUp(), hard code for FlexLib a track
reserve of one when trying to move up.
In FlexLib, the router promotes too easily METAL2 towards METAL4,
clogging the higher level. So we end up with the METAL2 level
under-saturated and the METAL4 over saturated, leading to routing
failures.
Now we assume that there is "one track less available" in METAL4.
As for now, solves the problem for LibreSOC.
* New: In CRM::GdsSteam::makeExternals(), now take into accounts Pad
for Net external components. Also delete the original components
after creating the copy in the right Net.
So now the PLL terminals are correctly seen.
* Bug: In NetBuilderHV::_do_xG_1PinM2(), for METAL2 pins on the EAST
side, we were computing the track from the XMax position of the
GCell. Now, with complete discoupling of the routing pitches and
GCell size, this is most of the time false.
Replace with a true computation of the last track of routing
area.
* Bug: In TrackSegment::getFreeInterval(), if, for whatever reason,
a discrepency happens between the TrackSegment and the Track,
that is the _track fields point to a *wrong* Track. Then the
index lookup will fail (Track::npos), so return an all-span
interval instead of trying to expand it and crash (out of
bound).
* Bug: In NetBuilderHV::_do_xG_1PinM2(), when the M2 pin is on the *east*
side and there are three globals, we must swap htee1 & htee2.
Otherwise, we the SW/NE contacts do not have the right numbers
of free segments attach.
* New: In AnabaticEngine::cleanupGlobal(), check that no global component
is left behind, sure sign that the global to detailed building went
wrong.
* Bug: In Etesian::HFNS::Cluster, all the created nets were systematically
created in the IN direction, which is obviously wrong for the driver.
Now Slice::raddTransPlug() accept a third argument stating if we are
creating a driver or a sink. Direction of the net is now combining
and can be IN, OUT or sometimes INOUT.
The VHDL files where reflecting that problem and made GHDL choke.
* Change: In Etesian::HFNS::Cluster, prefix the instance name by "cmpt_"
so it doesn't clash with the signal name in VHDL.
* Bug: In Etesian::Placement::Slice::fillHole(), do not use the xmin
previous bound, but pitch it (by excess). Insert ties *only* if
they completely fit in the free space.
This bug was showing *between* two SRAMs side-by-side, a column
of tie was inserted...
* Bug: In cumulus/plugins.block.block.py, always import Python modules
using the exact same path. Otherwise the module may get imported
twice and static variables are duplicated, generating a big mess.
This was causing problem for the LUT in macro.py, and got SRAMs
blocks encapsulated twice.
* New: In cumulus/plugins.block.block.Block.addPlaceHolder(), create
a "place holder" instance over a given area to prevent the placer
from using it. Allow to make space reservation.
* New: In cumulus/plugins.block.configuration.BlockConf, copy the
toXPitch() and toYSlice() methods from spare in order to share
them between modules. Still have to remove some other local copies.
* New: In cumulus/plugins.block.spare.QuadTree, keep a list of all
the X centers of the partitionned areas. For yse by the power lines.
* New: In cumulus/plugins.chip.chip, move doPowerLayout() call from
doChipFloorplan() to doConnectCore(), this is to delay the call
until *after* the spare QuadTree has been created and we can
align the power lines to the centers of the QuadTree.
* New: In cumulus/plugins.chip.pads.Corona.doPowerLayout(), if a
spare QuadTree has been created, align the power lines on the
X center of the leaf areas. This is a cheap way to avoid DRC
errors between the power BigVias and the wires from the various
clock trees (on METAL5).
* New: In cumulus/plugins.block.macro, add an ad-hoc patch for Staf's
SRAMs. The blockage areas are slightly too narrow. We enlarge
them by one pitch.
Jean-Paul Chaput
Luke Kenneth Casson Leighton