Commit Graph

354 Commits

Author SHA1 Message Date
Jean-Paul Chaput 9c7770806c Change of loading order in LefImport, now GDS first then LEF.
* Bug: In LefImport::_macroCbk(), the GDS file must be loaded *before*
    we start putting nets & components from the LEF file. The GDS parser
    must find an blank slate and not try to modifies nets already
    created by LEF.
      This way, we really can modify the GDS layout to suit the LEF
    statements.
      Note that we may end up with two set of terminal exactly overlapping,
    a Pad from the GDS and a Segment from LEF.
2023-07-28 10:45:07 +02:00
Jean-Paul Chaput bec7bba938 Prevent the GdsParser to create rubbers.
* Change: In GdsParser::xyToPath(), we were creating articulated layout
    segments over contacts using the "all_nets_merged_in_gds" common net.
    But some segment may later be promoted to interface, that means
    deleting the previous one and re-creating it with the right
    external net.
      The deletion was automatically creating a rubber between it's two
    Contact anchors. And we there is no way to get rid of it (other than
    also removing the Contacts).
2023-07-28 10:45:07 +02:00
Jean-Paul Chaput 96f41776a8 In GdsStream & LefImport, thorough verification that coordinates are on foundry grid. 2023-07-22 16:40:00 +02:00
Jean-Paul Chaput e470ca8375 In RoutingLayerGauge::getTrackIndex() display position as physical unit. 2023-07-22 16:34:41 +02:00
Jean-Paul Chaput 892661ca2a Support of the FOREIGN directive in LEF files (using GDS view).
* New: In LefImport, add setGdsForeignDirectory() to point out from where
    to load the extra GDS file in case a FOREIGN directory is present
    in MACRO.
      Also add support for merging the supply nets. It may happens that
    the supply nets have different names in the GDS ("vdd!") and LEF files
    ("pvdd"), in that case, the LEF name supersede the GDS one.
      The GDS file will be loaded *first* then completed by the LEF contents.
      Blockage in the GDS file are *not* loaded.
* Change: In GdsParser, perform an early recognition of supply nets. For now
    it's hardwired to names starting by "vdd" and "gnd", but should be
    parametrized in the future.
      Needed for the LefImport to merge, if needed, the power supplies.
      In GdsStream::xyToComponent(), skip the blockage if required.
2023-07-19 16:06:43 +02:00
Jean-Paul Chaput bf5d4e881d More aggressive detection of supply pin in LefImport.
* Change: In LefImport::_pinCbk(), if a pin has "USE POWER" or "USE GROUND"
    make it a global signal (previously flagged only "!" appended to name).
* Change: In LefImport::_pinStdPostProcess() do not try to find "on grid"
    components for supply nets, just make all their components externals.
2023-07-17 15:04:12 +02:00
Jean-Paul Chaput 9d98c9aafd Allow Rectilinear to be tagged as external components in GdsParser. 2023-07-15 21:24:38 +02:00
Jean-Paul Chaput 73265c2d68 Quick and DRC unclean hack to manage rectilinear in LefImport. 2023-07-03 20:00:58 +02:00
Jean-Paul Chaput 014ec72652 First merge of coloquinte2 & tramontana branches.
Needed to merge thoses two branches as I needed to to uses features
from each other to implement GF180MCU.
2023-06-25 18:11:18 +02:00
Jean-Paul Chaput 04410f1cc2 Added support for GF180MCU, part 1.
* New: In LefImport::LefParser, add support for LEF Polygons that are
    translated into Hurricane Rectilinears.
* Change: In LefImport::setMergeLibrary(), the default behavior for the
    LEF parser is to create a new separate library under LEF/<lib_name>
    for each file. But if the various cells are put each one in it's own
    cell, this is suitable. So we can now set a library beforehand into
    which they will be all put.
* New: in CRL/technos.node180.gf180mcu, configuration files for the
    GF180MCU open PDK.
* New: in cumulus/designflow.technos, added a setupGF180MCU_GF() to
    initialize the GF PDK.
2023-06-22 14:13:19 +02:00
Jean-Paul Chaput 5afb4cabe9 Add a verbose option to ToolEngine, don't always display infos. 2023-03-28 16:06:49 +02:00
Jean-Paul Chaput 1557d613ae Comprehensive reorganisation of the Python part of Coriolis.
* Move all Python stuff under a common Python namespace "coriolis".
* Instead of having a series subtrees for each tool, integrate
  everything in one common tree. So now, all components can be
  located either with an absolute path from "coriolis" or, inside
  cross-reference themselves through relatives imports.
* As a consequence, we only need to add ".../site-packages/coriolis/"
  to the PYTHONPATH, and not a whole bunch of subdirectories.
  And nothing, if installed in-system.
* The tree of free technologies configuration files is also moved
  below "coriolis/technos" instead of "/etc".
* Supressed "cumulus" level for the plugins.
* All python modules are rewritten using relative imports except
  for the configuration files that uses absolute import as they
  can be cloned outside of the tree to serve as templates.

* Change: In boostrap/FindPythonSitePackages, include "/coriolis" in
    Python_CORIOLISARCH and Python_CORIOLISLIB.
      Provide a Python_SITELIB *without* "/coriolis" appended.
* Change: In cumulus/plugins/__init__.loadPlugins(), must prefix modules
    read in the plugins directory by "coriolis.plugins.". No longer need
    to add their path to sys.path.
* Change: In crlcore/python/technos/nodeX/*/devices.py, the scripts of
    the layouts generators must be prefixed by "coriolis.oroshi.".
* Change: In CRL::System CTOR, no longer add the pathes of the various
    plugins to sys.path. Only "site-packages/coriolis/".
* New: In Utilities::Path::toPyModePath(), new method to convert a
    filesystem path into a python module path.
      Examples:
        "coriolis/plugins/block"    --> "coriolis.plugins.block".
        "coriolis/plugins/rsave.py" --> "coriolis.plugins.rsave".
* Change: In katanaEngine::_runKatanaEngine(), rename the hook script
    initHook.py. No longer need to modify sys.path.
* Change: In BoraEngine::_runBoraEngine(), rename the hook script
    initHook.py. No longer need to modify sys.path.
* Change: In UnicornGui::_runUnicornInit(), rename the hook script
    initHook.py. No longer need to modify sys.path.
* Change: In cumulus.plugins.chip.constants, put the constants
    outside __init__.py to avoid a loop at initialization.
2023-02-27 22:14:32 +01:00
Robert Taylor a02c88a893 Don't link libpython, it isn't there in manylinux 2023-02-21 16:10:55 +01:00
Robert Taylor 5a669c4641 Fix Python linking issues 2023-02-21 16:10:55 +01:00
Jean-Paul Chaput d2b40d568b Extend routing gauge to support non-routing layers at the bottom.
* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
    - Unusable : just do nothing with it, but the layer is stacked.
    - BottomPowersupply : can be used for supply routing only, and
      is *below* the normal routing layers (instead of on top as
      usual).
    Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
    to give the index (depth) of the first layer usable for routing.
    (not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
    the initial wiring, provides (Session) and use (NetBuilder) the
    new functions:
      - getBuildRoutingLayer(depth)
      - getBuildContactLayer(depth)
      Thoses functions takes into account (offset) the unusable layers
    so depth 0 is the first usable routing layer, and so on.
2023-01-07 12:51:38 +01:00
Jean-Paul Chaput 2501688dd1 Add support for layers alias names. Bug in _addPhysicalrule().
* New: In Technology, in order to support symbolic technology on top
    of a real technology using non-generic layer names, it comes in
    handy to be able to define layer alias names. Generic *real*
    layer names could be defined as alias over the technology
    specific ones. Then, we can build the symbolic layers upon
    the generic names (so *that* part of the init code can be
    shared between techs).
       Adds Technology::addLayerAlias()
       The semantic of Technology::getLayer() changes a little, it
     return the techno layer associtated to the name *or* the
     aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
    we were using it's name *after* the deletion of the rule object.
    Nasty crash.
      Improve the error message by giving the name of the conflicting
    rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
    analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
    line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
    from the technology. From generic names to actual technology
    layer names.
       Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
    the layers names translated.
2023-01-05 16:58:49 +01:00
Jean-Paul Chaput ae01be3c53 Set the initial verbose levels to off. Smarter loadUserSettings(). 2022-12-31 14:50:46 +01:00
Jean-Paul Chaput c131e7a948 Clean parameters for routing topologies. Improved 2RL- support.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :

1. The routing gauge itself (tells which layers are in which
   directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
   Currently we support:
   * "HV,3RL+", for all SxLib derived standard cells.
   * "VH,2RL", for hybrid routing (over the cell, but terminals
     are also in the first RL).
   * "2RL-", for strict channel routing.
   * "VH,3RL+", an attempt for FreePDK 45, not optimized enough
     to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
   built.
   * VH      : first RL is V.
   * HV      : first RL is H.
   * OTH     : Run in full over-the-cell mode (needs at least 3RL).
   * Channel : Run in *strict* channel routing mode (no routing over
               the standard cells).
   * Hybrid  : Create channels, but can use H tracks over the
               standard cells.

Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.

* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
    layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
    always returning false when the gauge was 2RL only. Now, check
    on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
    there was a bad computation of the deep RLs when the top layer
    was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
    in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
    policy to converge on Arlet6502. Always ensure that there is
    a 50% ratio between terminal used V-tracks and free ones.
      If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
    class of AnabaticEngine.  They uses Anabatic::Configuration
    and Katana::Configuration that also derives from each other.
    I though I had made one configuration attribute in the base
    class that was using the right Configuration. But no. I did
    have two configurations attributes, one in AnabaticEngine and
    one in KatanaEngine, the later "shadowing" the former. As a
    results, parameters modified in AnabaticEngine, *after* the
    initial creation of the tool *where never seen* at Katana
    level (due to it's own duplicate). What a mess.
      Now there is only one attribute in the *base* class Anabatic,
    which is created through a new virtual function _createConfiguration()
    called in _postCreate() which allocate the right Configuration
    according to the dynamic type of the tool (KatanaEngine).
      In KatanaEngine, access the configuration through the
    attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
    (which is not accessible anyway) but the getConfiguration() accessor.
    The accessor perform a static_cast from the Super::getConfiguration()
    into Katana::Configuration.
      Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
    of the requested NetBuilderStyle. The NetBuilderStyle is just a
    string that will be matched against the (hard-coded) supported
    NetBuilders. Then check the topological characteristics against
    the capabilities of the gauge (HV, VH and so on).
      Still a bit too hard-coded for now.
      This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
    topology and routing style:
      - _netBuilderStyle to explicitely select the NetBuilder to use.
        It's a string, which is provided by each NetBuilder.
      - _routingStyle to define how the overall routing will work.
        It's a set of flags (StyleFlags):
	* VH      : first RL is V.
	* HV      : first RL is H.
	* OTH     : Run in full over-the-cell mode (needs at least 3RL).
	* Channel : Run in *strict* channel routing mode (no routing over
	            the standard cells).
	* Hybrid  : Create channels, but can use H tracks over the
	            standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
    should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
    saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
    doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
    terminals where created *twice*. Uterly stupid, there where placed in
    overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
    RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
    they are in the same GCell, only do one (the conflicting interval)
    is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
    when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
    *strict channel* style and *hybrid* style. Tag the GCells as std cells
    row or channels only in the former case.
2022-11-26 13:07:12 +01:00
Jean-Paul Chaput 13795bec48 Add Environement attribute (pattern) to match the FF names. 2022-10-31 16:31:30 +01:00
Jean-Paul Chaput a0880da706 Issue a warning when the blockage net (for OBS) do not exists. 2022-10-31 16:29:07 +01:00
Jean-Paul Chaput 3613ce0b5d Typo in LefImport, the conf variable name is "lefImport.unmatchedlayers". 2022-10-30 10:08:43 +01:00
Jean-Paul Chaput dbfcfae1e8 Update of the DefExport (work in progress).
* New: In CRL::DefExport, checkStatus() has a second argument to display
    a more comprehensive error message.
      Applied throughout all the DEF callbacks.
* Bug: In CRL::DefExport, the UNIT statement and associated toDefUnits()
    functions where wrong. Now always use a UNITS of 1000 in microns.
    Then toDefUnits() converts DbU into microns and multiply by 1000.
* Change: In CRL::defExport::_netCbk(), enable the net name renaming
    only when the ProtectNetNames flag is set.
* New: In CRL::PyDefExport, also export the flag values to Python.
2022-10-27 19:47:17 +02:00
Jean-Paul Chaput 775b6bf1fc Better management of discrepencies bewteen LEF & techno layers.
* Change: In CRL::LefImport::LefParser, layers defined in the LEF file
    are matched *in order* to the ones from the technology *in order*
    (not by name matching). But if there is a mismatch, that is more
    layers in the techno than in LEF, we got a shift. Now we can tell
    the parser to ignore a set of layers by setting up the configuration
    variable:
       LefImport.unmatchedLayers = 'DIFFP,POLY2,SMURF'
2022-10-27 19:46:29 +02:00
Jean-Paul Chaput 81920c622e Stricter layer management in the GDS parser.
* In CRL::GdsStream::_staticInit(), all the layers where added to the
    translation table, whether or not they where configured for the
    GDS stream. So the non GDS configured layers got a GDS layer
    id of 0 and were using this case. Either overwriting the legit
    layer or creating a new one while it should have been invalid.
      Now we check for the hasGds() predicate of the layers.
* In CRL::GdsStream, add a new option to tell that, layer id 0,
    if undefined, may be used as the definition of the boudary of
    the cell (abutment box).
* In CRL::PyGds, now also export the flags to the Python interface.
2022-10-27 19:45:20 +02:00
Jean-Paul Chaput a6f61c1044 Update the channel routing feature to integrate with the OTC P&R.
* Update: In CRL/node600/phenitec/kite.py, update the routing gauge to
    the new format. So now we can use again SxLib-2M (channel routing
    SxLib for two metal technologies).
* Change: In CRL::BlifParser, if a master cell is not found in the
    AllianceFramework, then try in the Blif supplied libraries.
    This is used to load the zero, one and tie cells.
      Add a Blif::getCell() static function to look into the Blif
    supplied libraries.
* Change: In CRL::LefImport, sometimes there can be discrepencies between
    the LEF ROUTING layers and the Coriolis routing gauge. Now ignore
    routing layers that are *not* presents in the Coriolis gauge.

* Change: In AnabaticEngine, moved routingMode attribute from KatanaEngine,
    as some setup operations needs it.
* Change: In AutoSegment::canReduce(), allow fixed segments to be reduced
    if they are "jumpers" (turn+turn and top+top or bot+bot).
      This case arise on the edge of routing channels for fixed wires
    to connect terminals.
* Change: In AutoSegment::getTopologicalinfos(), compute differently the
    (leftBound,rightBound) interval when in channel mode.
       In over-the-cell mode, this interval is the one of the whole
    GCells under the wire. In channel mode, for fixed wires (that is,
    verticals connecteds to cells) this interval is reduced to half
    the GCell height, on the connected side of said channel.
      This allows Manipulator::_insertToTrack() to issue disantangling
    requests (push left/push right) for fixed segments that are face
    to face in the channel.
* Change: In Anabatic::Configuration CTOR, allow the cellGauge to have a
    different name from the routingGauge. Now if the cell gauge that
    should match the routing gauge is not found, fallback to the
    name set in "anabatic.cellGauge" parameter.
      Case occur when we try to match with CORE sites from LEF files.
* Change: In Etesian::Configuration CTOR, same change as in the
    Anabatic configuration.
* Change: In Anabatic::GCell::updateDensity(), never set the GoStraight
    flag in channel mode. This flag makes sense when there is at least
    4 routing layers (so we have 2 contiguous free of blockages).
* Bug: In Anabatic::Session::_getNearestGridpoint(), sometimes the nearest on
    grid point is outside the constraint box. Now force the point
    to remains inside constraints even if offgrid.

* Change: In Katana::DataNegociate::update(), perpandiculars that are
    either reduced or in non-preferred routing direction should not
    trigger a bug message.
* Change: In KatanaEngine::_check(), do not check for fixed, horizontal
    non-prefs AutoSegments in channel mode (avoid false bug display).
* Bug: In Manipulator::_forceToTrack(), slighty shrink (-1) the interval
    to free. The intersection function of intervals returns true when
    the two intervals *exactly* touches (1.vMax == 2.vMin). But in
    this specific case, they are not *overlapping* and no action
    should be taken...
* Bug: In Manipulator::_insertInTrack(), do not reject the track when
    we are overlapping a fixed vertical segment in channel mode.
    (Hmm, maybe already corrected by the previous one).
* Change: In Katana::NegociateOverlapCost(), in channel mode, do
    not put two overlaping vertical fixed segments into infinite cost.
    This happens when two cell connected verticals are face to face in
    a channel. We want them negociated the track (by shrinking their
    length) instead of excluding it right away.
* Change: In NegociateWindow::createTrackSegment(), in channel mode,
    do not attempt to create a track segment over a fixed and reduced
    AutoSegment.
      Do not attempt to put a non-preferred AutoSegment on a Track
    either.
* Bug: In RoutingEvent::revalidate(), the number of availables tracks
    was badly computed when in the pure constraint case, when there
    was only one it was reporting zero.
* Change: In TrackElements::TrackElements_Perpandicular::Locator,
    do not issue a bug when an non-pref or reduced AutoSegment do not
    have an associated TrackElement.
* Change: In TrackSegmentCost::update(), do not issue a bug when a
    perpandicular is reduded or non-pref and do not have a TrackElement.
2022-10-22 16:39:22 +02:00
Jean-Paul Chaput 1babec2e91 Save VHDL model only once in the rsave Cumulus plugin.
* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
    one instance of was encountered. Resulting in multiple saves.
    It was, of course, ineficient, but it also triggers a bug
    that seems to happen after multiple save : the VHDL additional
    property was deleted *before* the full hierarchical dump was
    finished.
      Now, we save each Cell only once so it does not occur, but
    should make a deeper investigation later.
2022-05-21 13:02:58 +02:00
Jean-Paul Chaput 59c0ab067b Mangle the "'" in Verilog to VHDL translator. 2022-05-12 17:52:22 +02:00
Jean-Paul Chaput 0a64f3b83d Create and connect dummy signals for unconnected *outputs* in BLIF parser. 2022-05-12 17:51:56 +02:00
Jean-Paul Chaput 921c519bd3 More detailed error message in case of VHDL PORT MAP discrepency. 2022-05-12 17:51:30 +02:00
Jean-Paul Chaput cd60032d9c Added direct management of macro blocks I/O pins in METAL2 & METAL3.
The decoupling of the cell gauge and the routing gauge implies that
the METAL2 & METAL3 terminals of macro blocks cannot be aligned on
the routing tracks anymore. That is, an horizontal METAL2 terminal
will not be on a track axis, but offgrid, so we no longer can use
a METAL2 horizontal segment to connect to it. Making an adjustement
between the offgrid terminal and the on-grid segment has proven
too complex and generating difficult configuration for the router.
Moreover, METLA2 terminal could be fully inside a METAL2 blockage.
So now, when the gauges are decoupled, we connect the METAL2 and
METAL3 the same way we do for METAL1: *from above* in the perpandicular
direction and using a *sliding* VIA. We assume that those kind of
terminals in upper metals are quite long.

* New: In Hurricane::Rectilinear, export the isNonRectangle() method
    to the Python interface.
* New: In CRL::RoutingGauge, add function isSuperPitched() with the
    associated boolean attribute. Set to true when each pitch of
    each layer is independant (not low fractional multiples).
* New: In AnabaticEngine, add the ability to temporarily disable the
    canonize() operation (mainly used in dogleg creation).
* New: In AutoSegment::canonize(), do nothing if the operation is
    disabled by AnabaticEngine.
* Bug: In Session::_revalidateTopology(), disable the canonization
    during the topology updating of a net. Too early canonization
    was occuring in makeDogleg() leading to incoherencies when
    performing the later canonization stage over the complete net.
    Mostly occured in the initial build stage of the net.
* New: In GCell, add function postGlobalAnnotate(), if a layer
    is fully blocked (above 0.9), typically, under a blockage,
    add a further capacity decrease of 2 on the edges. So we may
    handle a modicum of doglegs.
* Bug; In GCell::addBlockage(), removeContact(), removeHSegment()
    and removeVSegment(), forgot to set the Invalidated flag.
    This may have lead to innacurate densities.
* Change: In GCell::updateDensity(), more complex setting of the
    GoStraight flag. This flag is now set if we don't have two
    *contiguous* below 60% of density. We need free contiguous
    layers to make doglegs.
* New: In NetBuilder, now manage a current state flag along
    with the state flag of the *source* GCell. This flag is used
    to tell if the GCell needs it's *global* routing to be done
    using the upper layers (METAL4 & METAL5) instead of the
    lower ones.
* New: In NetBuilder::setStartHook(), set the state flag of the
    GCell to ToUpperRouting when processing a global routing
    articulation and one of the base layer is obstructed
    above 0.9.
      In GCell with terminals, also set ToUpperRouting when there
    are some in METAL2 / METAL3 and the gauge is not super-pitched.
* New: In NetBuilder, function isInsideBlockage(), to check if a
    terminal is completely or partially enclosed in a blockage.
* Change: In NetBuilderHV::doRp_AutoContact(), remove support for
    trying to put on grid misaligned METAL2/METAL3.
      Instead systematically access them from above.
      Do not cover with fixed protection terminals that are already
    enclosed in blockages.
* Bug: In NetBuilderHV::doRp_AutoContact(), always add the terminal
    contact in the requested GCell and not the target/source one,
    in case the terminal span several GCells.
* Change: In NetBuilderHV::doRp_Access(), create the local wiring
    according to the RoutingPad layer.
* Change: In NetBuilderHV::_do_xG(), _do_2G(),
    create the global wiring in upper layers, according to the
    ToUpperRouting flag.
* Change: In NetBuilderHV::_do_xG_xM3(), now delegate to
    _do_xG_xM3_baseRouting() and _do_xG_xM3_upperRouting() if the
    density at terminal level is above 0.5.
* New: NetBuilderHV::_do_xG_xM3_baseRouting() and
    _do_xG_xM3_upperRouting() separated function to manage the
    local routing.
* Change: In NetBuilder::_do_globalSegment(), if the currently
    processed GCell or it's source is in ToUpperRouting mode,
    move up the global segment. Do *not* use the moveUp() function
    which would create doglegs unwanted at this stage.
* New: In KatanaEngine::annotateGlobalGraph(), call postGlobalAnnotate()
    on the GCell after the blockages have been taken into accound to
    add the penalty.
* Bug: In Track::getPrevious(), correctly manage the 0 value for the
    index argument. Strange it didn't show earlier.
      Same goes for Track::expandFreeInterval().
2022-04-27 21:56:41 +02:00
Jean-Paul Chaput 4ffd91822f Added support for SPICE terminal ordering from .spi files.
After a Cell has been created in memory (by parsers or Python scripts)
we can annotate it with the Spice parser so it will know the right
order with which to create the subcircuit call ('x').

* New: In CRL::Spice::load(), add support to read the ".subckt" card
    and guess the right ordering for generating the 'x' (subcircuit
    card call).
* Bug: In Spice::SpiceBit & Spice::BitExtension, when a Net bit property
    is removed, if it's the currently cached property in BitExtension
    it may lead to a crash. So when a property is destroyed, we must
    also clear the cache (see remove(), clearCache() & onReleasedby()).
      I'm wary that this could also happen on other kind of cached
    extensions...
* New: In CRL::NamingScheme, new method vhdlToVlog() to translate back
    VHDL net name into Verilog. Currently only changes "()" into "[]".
    Used to generate the commented SPICE interface for Alliance compliance.
* Change: In Spice::Entity, previously all the ordering where removed
    between each run of the SPICE parser, but the orders read from
    SPICE file (mostly standard cells) must be kept. So add a flag
    ReferenceCell to prevent the removal by ::destroyAll().
2022-04-03 13:18:42 +02:00
gatecat 6c66208e0c def: Write route segments
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-12 14:14:15 +00:00
gatecat 9635cc3311 lef: Fix MANUFACTURINGGRID order
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-12 13:42:03 +00:00
gatecat c4ef465c41 def: Fix order of instance transforms
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 19:45:24 +00:00
gatecat 4250c5bec7 def: Fix export of pins
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 18:47:13 +00:00
gatecat a8dd84838b def: Fix export units for non-lambda processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat ddb684bfe1 defexport: Make it useful for real processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
gatecat 2f1caca812 lefexport: Make it useful for real processes
Signed-off-by: gatecat <gatecat@ds0.me>
2022-01-10 16:54:04 +00:00
Jean-Paul Chaput 9aaaf33e6e Manage more interrupt signals in CRL::System::_trapSig(). Display value. 2022-01-01 16:46:15 +01:00
Jean-Paul Chaput 67ca0997c3 Merge branch 'fix-blif-zero-one' into 'devel'
blif: Improve detection of zero/one net by requiring it to be external

See merge request vlsi-eda/coriolis!12
2021-12-11 21:07:18 +00:00
Jean-Paul Chaput ba2a74e35d Tweaked DEF support to load the Caravel harness.
* Bug: In CRL::BlifParser::Model CTOR, forgot to set the direction
    on auto-generated power supply global nets. So they were put
    in "linkage" in the VST files.
* New: In CRL::DefImport, add specific support for the Sky130/Caravel
    harness "user_project_wrapper".Mainly:
    - Do not fuse together "io_in" and "io_out" as a single net as
      they should (according to the DEF). So we can connect separately
      on each of them. We only allow one port for each net, as in VHDL.
2021-12-11 19:48:57 +01:00
Jean-Paul Chaput 2f0bf5456d Added Etesian to the measurment system.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
    if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
    by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
    "placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
    set of measures.
2021-12-11 19:47:24 +01:00
gatecat 3f08b3789f blif: Improve detection of zero/one net by requiring it to be external
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-10 19:17:03 +00:00
Jean-Paul Chaput df972b7250 Add Diode/Feed flags in Cell. Correct computation of Instance count.
WARNING: We are partially duplicating the informations pertaining
         to the Alliance catalog (stored in the Catalog property)
	 directly into the Cell. This is needed for Flexlib which
	 is not using the Alliance loading mechanim. Ideally the
	 Catalog information should be moved into the Cell.

* New: In Cell, add new state flags Diode, PowerFeed (in addition to
    Pad & Feed).
      Export flags setter/getter to Python. For Flexlib usage.
* Change: In AllianceFramework::getInstancesCount(), correctly skip
    Diode & Feeds based on Cell flags. Those flags must correctly
    be set in the various Flexlib_fix.py scripts.
2021-11-28 19:03:02 +01:00
Jean-Paul Chaput 7c0f1fcf58 Fairly compute the flat numbers of instances in a design.
* New: In AllianceFramework::getInstancesCount(), add a flag TerminalNetlist
    to stop recursion on "terminal for netlist" instance level. This is to
    avoid counting physical only or non-routed instances inside hard macros,
    like SRAM blocks. This was leading to an overstimation of the "size"
    in number of gates of the routing problem.
* Change: In KatanaEngine CTOR, call for the terminal for netlist number of
    gates...
2021-11-26 11:29:23 +01:00
Jean-Paul Chaput 10bd5510da Fix library linking problem for gcc 9 and above (Ubuntu 20/Debian 11).
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
    target_link_library(). No longer add dependencies to the C++ base
    library but instead either to the Python associated module or
    to the final binaries. This was inderectly causing the linking
    problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
    bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
    the Python destroy method.
2021-11-22 00:05:48 +01:00
Jean-Paul Chaput 95dd4ab8ff Add minimal DEF support to parse the Caravel harness for Sky130.
* New: In CRL::DefImport, the previous version of the parser was designed
    only to read pure netlists, no physical components. Now add features
    for:
    * VIA generate statements. Generated VIAs are created as Cell and
      then instaciated wherever they are needed. Alternative would be
      to duplicate it's contents so the original netlist is not changed.
      But would create lot more objects.
    * PIN, added support for basic physical shapes.
    * SPECIALNETS and their associated wiring (path callback).
    Note: (to myself) As the Path is created *before* the NET or SPECIALNET
          callback is called, we must create a temporary net to store
          the path components. This is the "__prebuild__" net which
          will be merged later with the actual net.
2021-11-06 11:51:39 +01:00
Jean-Paul Chaput 7cb8e20644 Merge branch 'build-fix' into 'devel'
Fix Coriolis build on Arch Linux

See merge request vlsi-eda/coriolis!7
2021-10-15 16:51:20 +00:00
Jean-Paul Chaput d6b01a557a Fix out-of-bound with short layers names in GdsDriver::GdsStream.
* Bug: In CRL::GdsDriver::GdsStream::operator<<(Cell*), when looking for
    layer names ending with ".pin", must also check that the string is
    at least 4 characters long.
2021-10-15 18:39:07 +02:00
Myrtle Shah 1dfa6aff67 Add missing "#include"s
Signed-off-by: Myrtle Shah <gatecat@chipflow.io>
2021-10-15 13:40:29 +01:00