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caravel/verilog/gl
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Kareem Farid d14035d8a2 gpio_signal_buffering rtl decaps 
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
 		2022-11-01 19:16:53 +02:00
..
__user_analog_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
__user_project_wrapper.v Modified all of the Makefiles to better handle the GL netlist simulations, 2021-12-03 17:13:53 -05:00
buff_flash_clkrst.v Revert "remove unpowered netlist" 2022-10-16 09:56:24 -07:00
caravan-signoff.v signoff views for caravan 2022-10-22 07:01:29 -07:00
caravan.v reharden: caravan 2022-10-22 02:52:02 -07:00
caravel-signoff.v update caravel with tying `porb_h_in` with `por_l_in` (#326) 2022-10-21 11:52:00 -07:00
caravel.v removed caravel-eco.v gl netlist and added the eco for porb_h_in in caravel.v 2022-10-24 17:58:50 +02:00
caravel_clocking.v reharden: caravel_clocking 2022-10-18 06:18:30 -07:00
chip_io.v ~ regenerate chip_io netlist to fix missing power pins from constant blocks 2022-10-12 11:40:05 -07:00
chip_io_alt.v Added gl netlists for chip_io_alt and gpio_signal_buffering_alt (#327) 2022-10-21 12:06:20 -07:00
constant_block.v Added constant block openlane files and powered gl and modified housekeeping config.tcl 2022-10-12 04:12:27 -07:00
digital_pll.v reharden: digital_pll 2022-10-18 07:07:32 -07:00
gpio_control_block.v reharden!: gpio_control_block 2022-10-10 05:42:29 -07:00
gpio_defaults_block.v Corrected the gen_gpio_defaults.py script so that it behaves 2021-12-29 15:42:41 -05:00
gpio_defaults_block_0403.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_defaults_block_0801.v Corrected the pull-up definition and revised the CSB definition to 2022-10-05 10:02:24 -04:00
gpio_defaults_block_1803.v Modified the GL netlists to match the layout for the GPIO defaults 2021-11-29 20:17:11 -05:00
gpio_logic_high.v harden gpio_control_block 2021-11-04 16:19:12 +02:00
gpio_signal_buffering.v gpio_signal_buffering rtl decaps 2022-11-01 19:16:53 +02:00
gpio_signal_buffering_alt.v gpio_signal_buffering rtl decaps 2022-11-01 19:16:53 +02:00
housekeeping.v update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
mgmt_protect.v Update Openlane views 2022-10-27 09:53:45 -07:00
mgmt_protect_hv.v Fix mgmt_protect_hv gate-level netlist 2021-12-07 13:38:30 +02:00
mprj2_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
mprj_logic_high.v [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
spare_logic_block.v [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
user_id_programming.v [DATA] Add gds/lef/maglef/gl views for the user_id_programming block 2021-11-15 18:17:32 +02:00
xres_buf.v [DATA] Add views for xres_buf 2021-11-15 18:07:02 +02:00