caravel/verilog/dv/cocotb/tests/uart
M0stafaRady e8870d6a8b fix errors for gate level 2022-10-12 10:29:56 -07:00
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uart.py fix errors for gate level 2022-10-12 10:29:56 -07:00
uart_loopback.c Add test uart_loopback 2022-10-06 03:12:44 -07:00
uart_rx.c fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); 2022-10-06 02:14:59 -07:00
uart_tx.c Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00