caravel/verilog/dv/cocotb/tests
M0stafaRady dce509ab11 update script and testbench top level to include sdf 2022-10-12 14:41:37 -07:00
..
bitbang update script and testbench top level to include sdf 2022-10-12 14:41:37 -07:00
common_functions move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
cpu move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
gpio fix errors for gate level 2022-10-12 10:29:56 -07:00
hello_world add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
housekeeping fix errors for gate level 2022-10-12 10:29:56 -07:00
irq move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
logicAnalyzer fix errors for gate level 2022-10-12 10:29:56 -07:00
mem move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
mgmt_gpio move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
sessions/session.bitbang_spi_i.vpd.tcl add folder to store important sessions 2022-10-12 02:03:06 -07:00
spi_master fix errors for gate level 2022-10-12 10:29:56 -07:00
temp_partial_test move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
timer move caravel.py, cpu.py ... to interfaces directory 2022-10-10 04:50:45 -07:00
uart fix errors for gate level 2022-10-12 10:29:56 -07:00