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__uprj_analog_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__uprj_netlists.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_analog_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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__user_project_wrapper.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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caravan.v
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Made the same corrections to caravan as were made to caravel
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2021-11-17 09:06:42 -05:00 |
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caravan_netlists.v
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Removed two references for single-macro verilog files that are no
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2021-11-15 17:53:48 -05:00 |
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caravan_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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caravel.v
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Fixed another missing line from the management protect block call
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2021-11-18 08:25:13 -05:00 |
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caravel_clocking.v
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[RTL] Move inverter from top level to HK
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2021-11-16 13:59:17 +02:00 |
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caravel_netlists.v
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Removed two references for single-macro verilog files that are no
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2021-11-15 17:53:48 -05:00 |
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caravel_openframe.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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chip_io.v
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Corrected the corner pad connections to vssd and vccd, which were
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2021-11-17 11:44:32 -05:00 |
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chip_io_alt.v
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Corrected the corner pad connections to vssd and vccd, which were
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2021-11-17 11:44:32 -05:00 |
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clock_div.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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defines.v
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Update storage testbench to work with one 2K block
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2021-11-12 17:14:21 +02:00 |
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digital_pll.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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digital_pll_controller.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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gpio_control_block.v
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(1) Corrected an error from a recent commit where the reset was
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2021-11-03 23:18:36 -04:00 |
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gpio_defaults_block.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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gpio_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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housekeeping.v
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[RTL] Move inverter from top level to HK
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2021-11-16 13:59:17 +02:00 |
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housekeeping_spi.v
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Modified the housekeeping SPI to generate a read strobe (or rather
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2021-10-23 22:06:24 -04:00 |
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mgmt_protect.v
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Revised the management protect block to include protections against
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2021-10-27 19:36:43 -04:00 |
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mgmt_protect_hv.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj2_logic_high.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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mprj_io.v
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Modified the padframe definition to keep the vccd domain continuous
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2021-11-03 10:53:09 -04:00 |
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mprj_logic_high.v
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Revised the management protect block to include protections against
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2021-10-27 19:36:43 -04:00 |
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pads.v
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Modified the padframe definition to keep the vccd domain continuous
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2021-11-03 10:53:09 -04:00 |
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ring_osc2x13.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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simple_por.v
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Seeding with documentation of pinout and verilog RTL (mostly unchanged
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2021-10-12 16:31:42 -04:00 |
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user_defines.v
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Split the layout of the GPIO defaults block into three versions, for the
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2021-11-06 13:28:26 -04:00 |
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user_id_programming.v
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Implemented a system for setting the GPIO power-on defaults through
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2021-10-23 17:18:30 -04:00 |
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xres_buf.v
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Renamed the poorly and awkwardly named "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped"
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2021-10-31 21:43:09 -04:00 |
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