mirror of https://github.com/efabless/caravel.git
91 lines
3.0 KiB
Verilog
91 lines
3.0 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`timescale 1 ns / 1 ps
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`define UNIT_DELAY #1
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`define USE_POWER_PINS
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`ifdef SIM
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`include "defines.v"
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`include "user_defines.v"
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`include "pads.v"
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/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
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`ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
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`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
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`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
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`include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
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`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
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`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
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`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
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`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
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`else
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`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
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`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
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`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
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`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
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`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
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`endif
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`ifdef GL
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// Assume default net type to be wire because GL netlists don't have the wire
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// definitions
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`default_nettype wire
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`include "gl/mgmt_core.v"
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`include "gl/digital_pll.v"
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`include "gl/DFFRAM.v"
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`include "gl/storage.v"
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`include "gl/user_id_programming.v"
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`include "gl/chip_io_alt.v"
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`include "gl/mprj_logic_high.v"
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`include "gl/mprj2_logic_high.v"
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`include "gl/mgmt_protect.v"
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`include "gl/mgmt_protect_hv.v"
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`include "gl/gpio_control_block.v"
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`include "gl/gpio_defaults_block.v"
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`include "gl/gpio_logic_high.v"
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`include "gl/xres_buf.v"
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`include "gl/caravan.v"
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`else
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`include "digital_pll.v"
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`include "caravel_clocking.v"
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`include "user_id_programming.v"
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`include "clock_div.v"
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`include "mprj_io.v"
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`include "chip_io_alt.v"
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`include "housekeeping_spi.v"
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`include "housekeeping.v"
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`include "mprj_logic_high.v"
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`include "mprj2_logic_high.v"
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`include "mgmt_protect.v"
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`include "mgmt_protect_hv.v"
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`include "gpio_control_block.v"
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`include "gpio_defaults_block.v"
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`include "gpio_logic_high.v"
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`include "xres_buf.v"
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`include "mgmt_core_wrapper.v"
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`include "caravan.v"
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`endif
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`include "simple_por.v"
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`endif
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