caravel/verilog/dv/cocotb
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
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doc add photo of cocotb structure 2022-10-02 14:10:17 +02:00
tests Add clock redirect test 2022-10-06 09:20:06 -07:00
wb_models/housekeepingWB Fix housekeeping spi tests 2022-10-02 05:37:27 -07:00
.gitignore remove hex files from directory 2022-10-02 04:20:32 -07:00
Makefile update make file to take user_project_wrapper file as input for iverilog 2022-10-02 06:48:29 -07:00
README.md update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00
caravel.py Add trial of test gpio_all_i_pu still not work 2022-10-05 08:22:51 -07:00
caravel_tests.py Add clock redirect test 2022-10-06 09:20:06 -07:00
caravel_top.sv add new test spi_master_rd 2022-10-03 05:36:36 -07:00
common.py Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
cpu.py add bitbang_spi_o tests 2022-10-01 12:39:54 -07:00
defsParser.py Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
logic_analyzer.py Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
pli.tab Adding cocotb evironment with tests and scripts to run 2022-09-30 03:52:34 -07:00
tests.json Add clock redirect test 2022-10-06 09:20:06 -07:00
verify_cocotb.py update verify_cocotb.py script to collect coverage only when -cov is passed 2022-10-06 04:44:55 -07:00

README.md

Overview

Cocotb environment (CTN) is a dynamic simulation testing environment. It's purpose is to speed testing simulation time and get coverage data. The environment is developed using cocotb, an open source coroutine-based co simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. CTN has 2 main layers: tests and whitebox models. Tests layer contain multiple tests and sequences that can communicate with the caravel (dut) through drivers shown in read at fig 1. Whitebox models layer contain multiple models that should mimic the behavior of each main block inside caravel see fig1. Model is supposed to check if the model is working as expected, if its registers contain the expected values all the time and report coverage of features provided by this block if its tested or not.

Alt text

fig1. caravel testbench environment (read lines are drivers )

Prerequisites

  apt update && apt install python3 python3-pip
  pip3 install cocotb
  pip3 install cocotb_coverage
  pip3 install coverage
  pip3 install cocotb-bus
  • iverilog or vcs

run a test

Use script verify_cocotb.py

  -h, --help            show this help message and exit
  
  -regression REGRESSION, -r REGRESSION
                        name of regression can found in tests.json
                        
  -test TEST [TEST ...], -t TEST [TEST ...]
                        name of test if no --sim provided RTL will be run
                        <takes list as input>
                        
  -sim SIM [SIM ...]    Simulation type to be run RTL,GL&GL_SDF provided only
                        when run -test <takes list as input>
                        
  -testlist TESTLIST, -tl TESTLIST
                        path of testlist to be run
                        
  -tag TAG              provide tag of the run default would be regression
                        name and if no regression is provided would be
                        run_<random float>_<timestamp>_
                        
  -maxerr MAXERR        max number of errors for every test before simulation
                        breaks default = 3
                        
  -vcs, -v              use vcs as compiler if not used iverilog would be used
  
  -cov, -c              enable code coverage
                        

Tests

Refer to tests.json for tests list

Directories names fixed for now

repo

caravel_mgmt_soc_litex/

caravel

verilog

dv cocotb

cocotb directory tree

├── caravel.py -> contains driving and mentoring functions for caravel interface
├── caravel_top.sv -> testbench top level 
├── cpu.py -> contains driving and mentoring functions for wishbone when disable the cpu 
├── hex_files -> folder that contains hex files 
├── verify_cocotb.py -> script that run tests and regressions 
├── sim ->  directory get generate when run a test
│   └── <tag> -> tag of the run  
│       ├── <sim type>-<test name> -> test result directory contain all logs and wave related to the test
│       ├── command.log -> command use for this run 
│       └── runs.log -> contains status of the run fails and passes tests 
├── tests -> directory contains all the tests 
├── tests.json -> test list have all the tests, regressions and contain small description about every test 
└── wb_models -> contains checkers and models for some caravel blocks