caravel/verilog/dv
M0stafaRady 28b453783f Add clock redirect test 2022-10-06 09:20:06 -07:00
..
caravel Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
cocotb Add clock redirect test 2022-10-06 09:20:06 -07:00
wb_utests Introduction of PDK variable (#39) 2022-04-08 09:05:58 -07:00
README.md adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00
dummy_slave.v adding user_project_wrapper empty files -- gds & lef 2021-12-16 12:29:35 -08:00

README.md

DV Tests

Organized into two subdirectories:

  • caravel: contains tests for both the mangement SoC and an example user project.
  • wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
├── caravel
│   ├── mgmt_soc
│   ├── user_proj_example
└── wb_utests