caravel/verilog/dv/cocotb/tests
M0stafaRady 11330823b7 Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
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bitbang Add bitbang_spi_i test 2022-10-02 08:38:00 -07:00
common_functions increase the clock period to 25ns 2022-10-01 02:52:30 -07:00
cpu add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
gpio add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
hello_world add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
housekeeping/housekeeping_regs Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
irq fix bug at IRQ_uart 2022-10-03 09:49:51 -07:00
mem add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
mgmt_gpio add new test mgmt_gpio_bidir 2022-10-03 08:56:46 -07:00
spi_master Add hk_regs_wr_wb_cpu test 2022-10-04 03:24:15 -07:00
temp_partial_test add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
timer add clock to the output od configuration function 2022-10-01 12:34:53 -07:00
uart fix timeout values to the passing number of cycles required + 10% 2022-10-01 04:11:46 -07:00