10 Commits

Author	SHA1	Message	Date
M0stafaRady	688429eeda	move caravel.py, cpu.py ... to interfaces directory	2022-10-10 04:50:45 -07:00
M0stafaRady	8e72d5e13e	Add test uart_loopback	2022-10-06 03:12:44 -07:00
M0stafaRady	6830c79ae8	fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX);	2022-10-06 02:14:59 -07:00
M0stafaRady	a6e7b46128	delete reading from uart register in uart_rx test	2022-10-05 15:07:38 -07:00
M0stafaRady	78613c95cc	increase timeout for uart_rx and add uart_ev_pending_write	2022-10-05 15:02:07 -07:00
M0stafaRady	b31efbdeea	IO[0] affects the uart selecting btw system and debug	2022-10-05 13:47:23 -07:00
M0stafaRady	555488c832	fix timeout values to the passing number of cycles required + 10%	2022-10-01 04:11:46 -07:00
M0stafaRady	9615629a42	fix bug bit time calculation	2022-10-01 02:53:24 -07:00
M0stafaRady	18b4f36525	add test uart_rx	2022-10-01 02:23:47 -07:00
M0stafaRady	add4c5f6c8	Adding cocotb evironment with tests and scripts to run	2022-09-30 03:52:34 -07:00